Altera Arria V Hard IP for PCI Express - Manual (Page 148)

7–50 Chapter 7: IP Core Interfaces
Physical Layer Interface Signals
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
1 In all figures channels and PLLs that are gray are unused.
For variants that do not use all the channels in a bank, you can the other channels for
other protocols if your design meets one of the following two conditions:
■ The data rate and clock specification exactly match the PCI Express configuration
in which case you would route the CMU clock to all channels.
or
■ You can use the ATX PLL to provide clocks to the other channels.
The following figure shows channel utilization for Gen1 and Gen2 variants using the
ATX PLL. The ×8 variant is only available for Gen1.
Figure 7–36. Channel Placement Using CMU PLL
&K
&K
&K
&K
&K $7;3//
&083// $7;3//
3&,H+DUG,3
&K
&K
&K
&K
&K
&K
&K
$7;3//
&083//
3&,H+DUG,3
$7;3//
&K
&K
&K
&K
&K
&K
&K
&K
&K
$7;3//
&083//
$7;3//
&K
&K
&K
&K
&K
&K
&K
&K
&K
&K
3&,H+DUG,3
&K
&K
&K
&K
&K
&K
&K
&083//
&K
$7;3//
&K $7;3//
3&,H+DUG,3
[
[
[
[
&K