Altera Arria V Hard IP for PCI Express - Manual (Page 74)

5–10 Chapter 5: Parameter Settings for the Avalon-MM Arria V Hard IP for PCI Express
Avalon to PCIe Address Translation Settings
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Avalon to PCIe Address Translation Settings
Table 5–11 lists the Avalon-MM PCI Express address translation parameter registers.
Table 5–11. Avalon Memory-Mapped System Settings
Parameter Value Description
Number of address
pages 1,2,4,8,16,32,64,
128,256,512
Specifies the number of pages required to translate Avalon-MM addresses
to PCI Express addresses before a request packet is sent to the Transaction
Layer. Each of the 512 possible entries corresponds to a base address of
the PCI Express memory segment of a specific size.
Size of address
pages
4 KByte –4 GBytes
Specifies the size of each memory segment. Each memory segment must
be the same size. Refer to
“Avalon-MM-to-PCI Express Address Translation
Algorithm” on page 6–20 for more information about address translation.