Altera Arria V Hard IP for PCI Express - Manual (Page 189)

December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
10. Transaction Layer Protocol (TLP)
Details
This chapter provides detailed information about the Arria V Hard IP for PCI
Express. TLP handling. It includes the following sections:
■ Supported Message Types
■ Transaction Layer Routing Rules
■ Receive Buffer Reordering
Supported Message Types
Table 10–1 describes the message types supported by the Hard IP.
Table 10–1. Supported Message Types (2) (Part 1 of 3)
Message
Root
Port
Endpoint
Generated by
Comments
App
Layer
Core
Core (with
App Layer
input)
INTX Mechanism Messages
For Endpoints, only INTA messages are
generated.
Assert_INTA Receive Transmit No Yes No
For Root Port, legacy interrupts are translated
into message interrupt TLPs which triggers
the
int_status[3:0] signals to the
Application Layer.
■ int_status[0] : Interrupt signal A
■ int_status[1] : Interrupt signal B
■ int_status[2] : Interrupt signal C
■ int_status[3] : Interrupt signal D
Assert_INTB Receive Transmit No No No
Assert_INTC Receive Transmit No No No
Assert_INTD Receive Transmit No No No
Deassert_INTA Receive Transmit No Yes No
Deassert_INTB Receive Transmit No No No
Deassert_INTC Receive Transmit No No No
Deassert_INTD Receive Transmit No No No
Power Management Messages
PM_Active_State_Nak Transmit Receive No Yes No
PM_PME Receive Transmit No No Yes
PME_Turn_Off Transmit Receive No No Yes
The pme_to_cr signal sends and
acknowledges this message:
■ Root Port: When pme_to_cr is asserted,
the Root Port sends the PME_turn_off
message.
■ Endpoint: When pme_to_cr is asserted,
the Endpoint acknowledges the
PME_turn_off message by sending a
pme_to_ack message to the Root Port.
PME_TO_Ack Receive Transmit No No Yes
December 2013
UG-01110-1.5