Transceiver clock signals, Transceiver clock signals –7 – Altera Arria V Hard IP for PCI Express User Manual

Page 187

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Chapter 9: Reset and Clocks

9–7

Clocks

December 2013

Altera Corporation

Arria V Hard IP for PCI Express

User Guide

Transceiver Clock Signals

As

Figure 9–5

indicates, there are two clock inputs to the PHY IP Core for PCI Express

IP core transceiver.

■

refclk

—You must provide this 100 MHz or 125 MHz reference clock to the Arria

V Hard IP for PCI Express IP core.

■

reconfig_clk

—You must provide this 100 MHz or 125 MHz reference clock to the

transceiver PLL. You can either use the same reference clock for both the

refclk

and

reconfig_clk

or provide separate input clocks. The PHY IP Core for PCI

Express IP core derives

fixedclk

used for receiver detect from

reconfig_clk

.

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