Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board - Manual (Page 38)

2–28 Reference Manual Altera Corporation
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006
FPGA Configuration Block
FPGA
Configuration
Block To enable the highest configuration flexibility while maintaining the
lowest-cost and lowest-component usage, the on-board Stratix II GX
device can be configured in one of two ways:
● JTAG configuration
● Active serial configuration using an EPCS64 device
JTAG Configuration
The Stratix II GX device can be configured after power is applied to the
board. The JTAG interface permits the Quartus
® II software to load the
Stratix II GX device with a user design through an Altera download
cable. The user design remains in the Stratix II GX device until power is
removed from the board.
1 The JTAG configuration scheme bonds the JTAG ports to a set of
header connections. This scheme allows direct device
configuration as well as support for the Altera SignalTap
® II
embedded logic analyzer for debugging and logic probing.
Active Serial Configuration Using EPCS64 Device (U22)
The active serial configuration scheme uses a serial configuration device
(EPCS64), allowing the board to support the out-of-the-box experience.
The demo design and the Nios II embedded processor’s user code are
stored on the EPCS64 device and automatically configure the
Stratix II GX device upon power-up. If the load is not successful, the
CONF DONE LED (D14) does not illuminate and the Stratix II GX device
is not configured. If the load is successful, the CONF DONE LED
illuminates. See
Figure 2–18 .