Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board - Manual (Page 8)

1–2 Reference Manual Altera Corporation
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006
General Description
Board Component Blocks
The board provides the following major component blocks:
■ Flexible clock management system
● Four high-speed clock oscillators to support a variety of
protocols:
• 156.25 MHz
• 25, 100, 125, and 200-MHz from the clock generator
• 50 MHz
● SMA connectors for clock input and output
■ High-speed I/O & SMA connectors
● SMA connectors for high-speed interfaces
● Six channels of transmit differential output and six channels of
receive differential input at up to 6.375 Gbps
■ Power-supply management
● 5-V, 3.3-V, and 1.2-V switching regulators
● 3.3-V and 1.5-V/1.2-V linear regulators
■ USB interface
● Operates like a COM port on a host PC
● Eliminates the need for:
• Full USB software and hardware implementation
• USB software driver
■ General user-interface
● Debugging header
● LEDs
● 7-Segment LEDs
● Push-buttons
● DIP switches
■ Thermal management
■ Flash memory
● 56-pin TSOP package
● Compliant with common Flash interface (CFI)
● Reduces development time when used with the Altera SOPC
Builder CFI controller module
■ FPGA configuration
● JTAG interface header
● Active serial configuration scheme using EPCS64 device
• Configures Stratix II GX device on power-up