Zilog EZ80F916 - Manual (Page 37)

eZ80
®
CPU
User Manual
UM007715-0415 Memory Mode Switching
28
Because the CPU core resets to Z80 MEMORY mode, a JP.LIL Mmn is recommended
for use near the beginning of source programs that run primarily in ADL MEMORY
mode.
JP
Mmn 1
JP
Mmn
assembles to
C3 nn mm MM
The starting program counter is PC[23:0]. Write the
3-byte immediate value {MM, mm, nn}, to
PC[23:0]. The ADL mode bit remains set to 1. The
ending program counter is PC[23:0] = {MM, mm,
nn}.
JP.LIL
Mmn 1
JP.LIL
Mmn
assembles to
5B C3 nn mm
MM
This operation is the same as the previous
operation. The .LIL extension does not affect
operation when beginning in ADL mode.
JP.SIS
mn 1
JP.SIS
mn
assembles to 
40 C3 nn mm
The starting program counter is PC[23:0]. Write the
2-byte immediate value {mm, nn}, to PC[15:0].
Reset the ADL mode bit to 0. The ending program
counter is {MBASE, PC[15:0]} = {MBASE, mm, nn}.
JP.SIL
Mmn
1 N/A An illegal suffix for this instruction.
JP.LIS
mn 1 N/A An illegal suffix for this instruction.
Table 16. JP (rr) Instruction
User Code
ADL
Mode Assembled
Code
Operation
JP
(rr) 0
JP
(rr)
assembles to
E9 or DD/FD
E9
The starting program counter is {MBASE,
PC[15:0]}. Write the 2-byte value stored in rr[15:0]
to PC[15:0]. The ADL mode bit remains cleared to
0. The ending program counter is {MBASE,
PC[15:0]} = {MBASE, rr[15:0]}.
JP.S
(rr) 0
JP.SIS
(rr)
assembles to
40 E9
or 40
DD/FD E9
This operation is the same as the previous
operation. The .SIS extension does not affect
operation when beginning in Z80 mode.
JP.L
(rr) 0
JP.LIS
(rr)
assembles to 
49 E9
or 
49 DD/FD E9
The starting program counter is {MBASE,
PC[15:0]}. Write the 3-byte value stored in rr[23:0]
to PC[23:0]. Set the ADL mode bit to 1. The ending
program counter is PC[23:0] = rr[23:0].
Table 15. JP Mmn Instruction (Continued)
User Code
ADL
Mode Assembled
Code
Operation