Zilog EZ80F916 User Manual
Page 84
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
75
RRC s
(HL)
CB 1E
* * 0
P
0 *
(IX/Y+d)
DD/FD CB dd
1E
r
CB 08-0F
RRCA
0F
— — 0
—
0 *
RRD
A[3:0] (HL)[3:0]
(HL)[3:0] (HL)[7:4]
(HL)[7:4] A[3:0]
ED 67
* * 0
P
0 —
RSMIX
MADL 0
ED 7E
— — — — — —
RST
n
(SP)
PC
if MADL = 1 {
(SP)
ADL
}
PC {0000h,n}
C7-FF
— — — — — —
SBC
A, s
A A – s – C
(HL)
9E
* * *
V
1 *
ir
DD/FD 9C-9D
(IX/Y+d) DD/FD 9E dd
n
DE
r
98-9F
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source
S
Z
H
P/V
N
C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.
CY
7
0
A
3
7 4
0
3
7 4
0 (HL)
A
CY
7
0
s