Zilog EZ80F916 - Manual (Page 403)

UM007715-0415 Index
eZ80
®
CPU
User Manual
394
Index
Numerics
16-MB address mode 1
16-MB linear addressing 1, 7
24-bit linear addressing 2, 6, 10, 37
24-Bit Registers 13
24-bit registers 2
64-KB address mode 1
8-bit data path 2
A
About This Manual vi
accumulator register 9
ADC A, (HL) 79
ADC A, (IX/Y + d) 81
ADC A, ir 80
ADC A, n 82
ADC A, r 83
ADC HL, rr 85
ADC HL, SP 87
ADD A, (HL) 88
ADD A, (IX/Y + d) 90
ADD A, ir 89
ADD A, n 91
ADD A, r 92
ADD HL, rr 94
ADD HL, SP 96
ADD IX/Y, rxy 97
ADD IX/Y, SP 99
ADD with Carry 79, 80, 81, 82, 83, 85, 87
ADD without Carry 88, 89, 90, 91, 92, 94, 96, 97,
99
Add/Subtract Flag 15, 382
ADDRESS AND DATA LONG mode 6
Address and Data Long Mode Bit 10
Address Generator 3
address translation 3
ADL 18
ADL bit 6, 7
ADL Bit, Mixed 10, 388
ADL MEMORY Mode 7
ADL Mode 13
ADL mode 2, 3, 6, 7, 8, 10, 12, 18, 20, 25, 26, 28,
31, 32, 33, 34, 35, 37, 38, 40, 41, 46, 48, 67, 72
ADL mode and Z80 mode 18
ADL mode applications 41, 44
ADL mode bit 6, 20, 26, 27, 28, 29, 31, 33, 37, 39,
40, 41
ADL Mode Bit, Interrupt Mode 0 Operation 39
ADL Mode Bit, Interrupt Mode 1 Operation 40
ADL Mode Bit, Nonmaskable Interrupt Operation
37
ADL mode code 18
All Uppercase Letters, Use of ix
Alternate Register Set 11, 13
alternate register set 9
ALU 2, 3
AND A, (HL) 100
AND A, (IX/Y + d) 102
AND A, ir 101
AND A, n 103
AND A, r 104
Arithmetic Logic Unit 3
assembly code vi
Assembly Language Source Program Example 52
Assembly of the Op Code Suffixes 24
B
backward compatibility 6
Bit b, (HL) 106
Bit b, (IX/Y + d) 108
Bit b, r 110
Bit Numbering ix
Bit Test 106, 108, 110
Braces viii
Brackets viii
C
CALL 35
CALL cc, Mmn 112
CALL instruction 4