Fluke Biomedical 875 Victoreen - Manual (Page 38)

Maintenance, Calibration, and Troubleshooting
ESC Board
5
Critical voltages in one of the two muting OP AMPS of U502 are:
Normal (Low Signal Level
5-7
) Channel Test ECS TEST
Pin 10 +2 V +12.88 V* +2 V
Pin 9 0 V 0 V +12 V*
(Muting voltage)
Pin 8 +13.7 V 13.7 V -9.8 V
* An especially high voltage (12.88 V) is place on pin 10 during the Channel Test to overcome
that is placed on pin 9 during the ECS Test. Muting is not desired during the Channel Test. Althoug
there is only a slight possibility that an automatically initiated ECS Test would take place during a
Channel Test, it is desired to eliminate even this slight possibility.
Conversely, during the ECS Test muting is definitely wanted, and the +12 V on pin 9 can ea
the +2 V on pin 10.
5.10 ESC Board (P/N 876A-1-92, Schematic 876A-1-3D)
The wave-shapes shown in Figure 5-1 should be sufficient for localization of malfunction on the ECS
board. Test points A to S are shown on 876A-1-3D. The wave-shapes at the lettered test point
drawn to the same time scale and also synchronized in time.
The wave-shape at the top of Figure 5-1 is the output at TP201. It is the main synchronizing wavesh
for the lettered wave-shapes, but it is drawn to a different time scale.
These wave-shapes are best used in connection with the discussion of the ECS circuitry.
CAUTION
Electrostatic discharge precautions should be
followed when servicing the ECS board, due to the
MOS FET devices located on it.
the +12 V
h
sily overcome
s are
ape