Guralp Systems CMG-SAM - Manual (Page 20)

Operator’s Guide CMG SAM & CMG CRM
4. MICROPROCESSOR
The system is designed around a low power, high performance 16bit microprocessor
(Hitachi H8/500 series). This features a large address space (1Mb - 16 *64k pages) for
data storage and manipulation and many integrated functions such as multiple timers
and serial i/o ports.
The modular (paged) structure of the processor architecture is used to advantage in the
modular design of the system, each module being assigned to a separate ‘page’. Each
module is associated with an ‘I/O’ function and can be simply added to the system at an
available page. Every module includes 32k of RAM, which is used for data buffering
and workspace for the module’s software.
An important feature of the system design is its ability to synchronise the sampling of
the analogue to digital converter to an external time reference so that data samples are
accurately time stamped (at the source). The microprocessor timebase serves as the
system time reference and can be synchronised and tuned to an external reference such
as GPS to maintain sampling accurately synchronised to UTC. To avoid the cost and
power consumption of multiple GPS receivers in larger arrays the systems can also be
synchronised to a centrally transmitted time reference using a scheme similar to that
employed by the National Radio Time Standards (WWV,MSF and DCF77). As this
only involves sending 2 characters per second it can utilise a low bandwidth, even half-
duplex link.
To achieve the high degree of timing precision required for a 24 bit digitiser system the
microprocessor timebase is run from a precision voltage controlled oscillator which is
software controlled from the external reference so that its frequency is accurately set
and maintained with temperature and ageing. The control is sufficiently accurate to
maintain precision sampling for long periods (several hours) in the absence of an
external reference once the system has stabilised.
All the timing functions are derived via the internal timer/counter channels from the
precisely set processor frequency so that sampling and time-stamping are accurately
maintained with reference to UTC. The system also automatically compensates for the
pure time delay introduced by the digital filtering/decimation of the DSP which
provides data output at different sample rates simultaneously.
The main microprocessor board incorporates a battery-backed Real-Time Clock and
RAM which is used to set the systems internal software clock at start-up independent of
the availability of the external time reference. The RAM is used to store system
parameters such as the optimum control voltage setting for the system timebase and the
system configuration.
The microprocessor module includes the (multi-tasking) system operating software in
EPROM on page ‘0’ with space for future expansion onto page 1 with additional ROM
and RAM. This module can also support either 128k or 512k of static RAM for system
workspace or data buffering depending on the system requirements (number of data
channels and sample rates).
The microprocessor serial port provides an interactive interface for system setup and
configuration.
Issue D March 2001 18