Intel pentium 4 processor – HP XU700 User Manual
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2 System Board
System Bus
accept another request. The MCH, as target device, then requests the bus
again when it is ready to respond, and sends the requested data packet. Up
to four transactions are allowed to be outstanding at any given time.
Intel Pentium 4 Processor
The Pentium 4 processor has several features that enhance performance:
•
Data bus frequency of 400 MHz.
•
Dual Independent Bus architecture, which combines a dedicated 64-bit
L2 cache bus (supporting 256 KB) plus a 64-bit system bus that enables
multiple simultaneous transactions.
•
MMX2 technology, which gives higher performance for media,
communications and 3D applications.
•
Dynamic execution to speed up software performance.
•
Internet Streaming SIMD Extensions 2 (SSE2) for enhanced floating
point and 3D application performance.
•
Uses multiple low-power states, such as AutoHALT, Stop-Grant, Sleep and
Deep Sleep to conserve power during idle times.
The Pentium 4 processor is packaged in a pin grid array (PGA) that fits into
a PGA423 socket (423-pin Zero Insertion Force or ZIF socket).
Processor Clock
The 100 MHz System Bus clock is provided by a PLL. The processor core
clock is derived from the System Bus by applying a “ratio”. This ratio is fixed
in the processor. The processor then applies this ratio to the System bus
clock to generate its CPU core frequency.
Bus Frequencies
There is a 14.318 MHz crystal oscillator on the system board. This frequency
is multiplied to 133 MHz by a phase-locked loop. This is further scaled by an
internal clock multiplier within the processor.
The bus frequency and the processor voltage are set automatically.
Voltage Regulation
Module (VRM)
One VRM is integrated on the system board complying with VRM
specification rev. 9.0. High-current and low voltage processors are
supported.
The processor requires a dedicated power voltage to supply the CPU core
and L2 cache. The processor codes through Voltage Identification (VID)
pins with a required voltage level of 1.30 V to 2.05 V. The VID set is decoded