Document Outline

• MicroBlaze Development Kit Spartan-3E 1600E Edition User Guide
  • Table of Contents
  • About This Guide
    • Acknowledgements
    • Guide Contents
    • Additional Resources
  • Introduction and Overview
    • Choose the Starter Kit Board for Your Needs
      • Spartan-3E FPGA Features and Embedded Processing Functions
      • Learning Xilinx FPGA, CPLD, and ISE Development Software Basics
      • Advanced Spartan-3 Generation Development Boards
    • Key Components and Features
    • Design Trade-Offs
      • Configuration Methods Galore!
      • Voltages for all Applications
    • Related Resources
  • Switches, Buttons, and Knob
    • Slide Switches
      • Locations and Labels
      • Operation
      • UCF Location Constraints
    • Push-Button Switches
      • Locations and Labels
      • Operation
      • UCF Location Constraints
    • Rotary Push-Button Switch
      • Locations and Labels
      • Operation
      • UCF Location Constraints
    • Discrete LEDs
      • Locations and Labels
      • Operation
      • UCF Location Constraints
    • Related Resources
  • Clock Sources
    • Overview
    • Clock Connections
    • Voltage Control
    • 50 MHz On-Board Oscillator
    • Auxiliary Clock Oscillator Socket
    • SMA Clock Input or Output Connector
    • UCF Constraints
      • Location
      • Clock Period Constraints
    • Related Resources
  • FPGA Configuration Options
    • Configuration Mode Jumpers
    • PROG Push Button
    • DONE Pin LED
    • Programming the FPGA, CPLD, or Platform Flash PROM via USB
      • Connecting the USB Cable
      • Programming via iMPACT
      • Programming Platform Flash PROM via USB
  • Character LCD Screen
    • Overview
    • Character LCD Interface Signals
    • Voltage Compatibility
    • Interaction with Intel StrataFlash
    • UCF Location Constraints
    • LCD Controller
      • Memory Map
      • Command Set
    • Operation
      • Four-Bit Data Interface
      • Transferring 8-Bit Data over the 4-Bit Interface
      • Initializing the Display
      • Writing Data to the Display
      • Disabling the Unused LCD
    • Related Resources
  • VGA Display Port
    • Signal Timing for a 60 Hz, 640x480 VGA Display
    • VGA Signal Timing
    • UCF Location Constraints
    • Related Resources
  • RS-232 Serial Ports
    • Overview
    • UCF Location Constraints
  • PS/2 Mouse/Keyboard Port
    • Keyboard
    • Mouse
    • Voltage Supply
    • UCF Location Constraints
    • Related Resources
  • Digital to Analog Converter (DAC)
    • SPI Communication
      • Interface Signals
      • Disable Other Devices on the SPI Bus to Avoid Contention
      • SPI Communication Details
      • Communication Protocol
    • Specifying the DAC Output Voltage
      • DAC Outputs A and B
      • DAC Outputs C and D
    • UCF Location Constraints
    • Related Resources
  • Analog Capture Circuit
    • Digital Outputs from Analog Inputs
    • Programmable Pre-Amplifier
      • Interface
      • Programmable Gain
      • SPI Control Interface
      • UCF Location Constraints
    • Analog to Digital Converter (ADC)
      • Interface
      • SPI Control Interface
      • UCF Location Constraints
    • Disable Other Devices on the SPI Bus to Avoid Contention
    • Connecting Analog Inputs
    • Related Resources
  • Intel StrataFlash Parallel NOR Flash PROM
    • StrataFlash Connections
    • Shared Connections
      • Character LCD
      • Xilinx XC2C64A CPLD
      • SPI Data Line
    • UCF Location Constraints
      • Address
      • Data
      • Control
    • Setting the FPGA Mode Select Pins
    • Related Resources
  • SPI Serial Flash
    • UCF Location Constraints
    • Configuring from SPI Flash
      • Setting the FPGA Mode Select Pins
      • Creating an SPI Serial Flash PROM File
      • Downloading the Design to SPI Flash
      • Downloading the SPI Flash using XSPI
    • Additional Design Details
      • Shared SPI Bus with Peripherals
      • Other SPI Flash Control Signals
      • Variant Select Pins, VS[2:0]
      • Jumper Block J11
      • Programming Header J12
      • Multi-Package Layout
    • Related Resources
  • DDR SDRAM
    • DDR SDRAM Connections
    • UCF Location Constraints
      • Address
      • Data
      • Control
      • Reserve FPGA VREF Pins
    • Related Resources
  • 10/100 Ethernet Physical Layer Interface
    • Ethernet PHY Connections
    • MicroBlaze Ethernet IP Cores
    • UCF Location Constraints
    • Related Resources
  • Expansion Connectors
    • Hirose 100-pin FX2 Edge Connector (J3)
      • Voltage Supplies to the Connector
      • Connector Pinout and FPGA Connections
      • Compatible Board
      • Mating Receptacle Connectors
      • Differential I/O
      • UCF Location Constraints
    • Six-Pin Accessory Headers
      • Header J1
      • Header J2
      • Header J4
    • UCF Location Constraints
    • Connectorless Debugging Port Landing Pads (J6)
    • Related Resources
  • XC2C64A CoolRunner-II CPLD
    • UCF Location Constraints
      • FPGA Connections to CPLD
      • CPLD
    • Related Resources
  • DS2432 1-Wire SHA-1 EEPROM
    • UCF Location Constraints
    • Related Resources
  • Schematics
    • FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header
    • RS-232 Ports, VGA Port, and PS/2 Port
    • Ethernet PHY, Magnetics, and RJ-11 Connector
    • Voltage Regulators
    • FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections
    • FPGA I/O Banks 0 and 1, Oscillators
    • FPGA I/O Banks 2 and 3
    • Power Supply Decoupling
    • XC2C64A CoolRunner-II CPLD
    • Linear Technology ADC and DAC
    • Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM
    • Buttons, Switches, Rotary Encoder, and Character LCD
    • DDR SDRAM Series Termination and FX2 Connector Differential Termination
  • Example User Constraints File (UCF)