Xilinx MIcroblaze Development Spartan-3E 1600E - Manual (Page 44)

42 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
www.xilinx.com UG257 (v1.1) December 5, 2007
Chapter 5: Character LCD Screen R
Once mastered, the LCD is a practical way to display a variety of information using
standard ASCII and custom characters. However, these displays are not fast. Scrolling the
display at half-second intervals tests the practical limit for clarity. Compared with the
50 MHz clock available on the board, the display is slow. A PicoBlaze processor efficiently
controls display timing plus the actual content of the display.
Character LCD Interface Signals
Table 5-1 shows the interface character LCD interface signals.
Voltage Compatibility
The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However,
the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The
LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by
the FPGA meet the 5V TTL voltage level requirements.
The 390: series resistors on the data lines prevent overstressing on the FPGA and
StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD
drives the data lines when LCD_RW is High. Most applications treat the LCD as a write-
only peripheral and never read from from the display.
Table 5-1: Character LCD Interface
Signal Name FPGA Pin Function
SF_D<15> T8 Data bit DB7
Shared with StrataFlash pins
SF_D<15:8>
SF_D<14> R8 Data bit DB6
SF_D<13> P6 Data bit DB5
SF_D<12> M16 Data bit DB4
SF_D<11> M15 Data bit DB3
SF_D<10> P17 Data bit DB2
SF_D<9> R16 Data bit DB1
SF_D<8> R15 Data bit DB0
LCD_E M18 Read/Write Enable Pulse
0: Disabled
1: Read/Write operation enabled
LCD_RS L18 Register Select
0: Instruction register during write operations. Busy
Flash during read operations
1: Data for read or write operations
LCD_RW L17 Read/Write Control
0: WRITE, LCD accepts data
1: READ, LCD presents data
LCD_RET E3
LCD_CS1 P3
LCD_CS2 P4