Xilinx MIcroblaze Development Spartan-3E 1600E - Manual (Page 27)

MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide 25
UG257 (v1.1) December 5, 2007 www.xilinx.com
Configuration Mode Jumpers R
The configuration mode jumpers determine which configuration mode the FPGA uses
when power is first applied, or whenever the PROG button is pressed.
The DONE pin LED lights when the FPGA successfully finishes configuration.
Pressing the PROG button forces the FPGA to restart its configuration process.
The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration
storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial
mode.
The 64-macrocell XC2C64A CoolRunner II CPLD provides additional programming
capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration
modes and loading the FPGA from the StrataFlash parallel Flash PROM. The CPLD is user-
programmable.
Configuration Mode Jumpers
As shown in Table 4-1 , the J30 jumper block settings control the FPGA’s configuration
mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual
jumpers to select the FPGA’s configuration mode and associated configuration memory
source.
Table 4-1: MicroBlaze Development Kit Board Configuration Mode Jumper Settings
(Header J30 in Figure 4-2 )
Configuration
Mode
Mode Pins
M2:M1:M0 FPGA Configuration Image Source Jumper Settings
Master Serial 000 Platform Flash PROM
SPI
(see
Chapter 12,
“SPI Serial
Flash”
)
001 SPI Serial Flash PROM starting at
address 0
BPI Up
(see
Chapter 11,
“Intel
StrataFlash
Parallel NOR
Flash
PROM” )
010 StrataFlash parallel Flash PROM,
starting at address 0 and
incrementing through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
M0
M1
M2
J30
M0
M1
M2
J30
M0
M1
M2
J30