Interphase Tech 4538 User Manual
4538 pmc
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Table of contents
Document Outline
- Contents
- List of Figures
- List of Tables
- List of Examples
- Using This Guide
- Hardware Description
- Overview
- The PowerQUICC II
- The PCI Bridge
- PowerSpan PCI Configuration Registers
- PowerSpan PCI Registers
- PowerSpan Processor Bus Registers
- PowerSpan DMA Registers
- PowerSpan Miscellaneous Registers
- PowerSpan I·O Registers
- Interrupt Pins and Doorbell Usage
- PCI to Local Interrupt (ATN)
- Local to PCI Interrupt (–INTA)
- Hardware and Software Resets Through the PowerSpan
- Local Space Access From PCI Memory Space
- Access to the FLASH EEPROM Through CompactPCI
- PCI Memory Space and I/O Space Access From the PowerQUICC II
- In-situ EPLDs Programming
- Serial EEPROM Connected to the PowerSpan
- Board Equipment Register
- Vital Product Data (VPD)
- Interphase-Specific Production Data and Boot Monitor Parameters
- The FLASH EEPROM Boot Memory
- The QuadFALC T1/E1/J1 Framer
- The Ethernet Transceiver
- TDM Bus Configurations
- 4538 Power-Up Initialization
- Programming the Peripherals
- Accessing the 4538 on the PCI Side
- PowerSpan Configuration by the PCI Host
- Controlling the 4538 Hardware and Software Resets
- Controlling the PCI-to-Local Interrupt
- Local to PCI Interrupt (–INTA)
- Local Space Access From PCI Memory Space
- Access to the FLASH EEPROM Through PCI
- Serial EEPROM Connected to the PowerSpan
- In Situ EPLD Programming
- Optimizing the PCI Bus Utilization
- Effective Ordering of the PCI Accesses
- PCI Deadlock Situations
- Connectors and Front Panel
- Mechanical Information
- Bibliography
- Glossary
- Index