Interphase Tech 4538 - Manual (Page 115)

Chapter 4: Accessing the 4538 on the PCI Side
4538 Hardware Reference Manual 93
In Situ EPLD Programming
Glue logic is implemented in some EPLDs that can be programmed in the field using the
PCI interface.
The EPLDs are in a daisy-chain configuration, which enables all of them to be programmed
at once. They can be programmed in-situ by the PCI host, using PowerSpan interrupts as
I/O pins. A jumper must be placed on board location JP1 to enable the programming (when
present, this jumper sets the ISP signal –ISPEN to its active state 0).
These devices are initialized by Interphase and keep their programming during power off.
The normal user should not need to reprogram them.
Optimizing the PCI Bus Utilization
The PCI maximum throughput of 266 MB/s is very difficult to reach. The actual throughput
can be very disappointing if certain principles are not followed. These principles are:
Avoid the reads. Prefer the writes. Writes can be very efficient, because they are posted
in the FIFOs included in the various PCI bridges. A read needs completion of the entire data
transfer from its origin to its destination, before being considered as finished. Because of
the arbitrations on the various local busses and because of resynchronizations occurring
each time there are different bus clocks, a single read can take approximately 1 µs.
Prefer the bursts. During a burst, the duration of the transfers after the first one can be very
efficient and last only one PCI cycle. On the 4538, only the PowerSpan DMAs can generate
efficient bursts, because they do transfers to incremental addresses.
Prefer DMA transfers. For data transfers between the PCI space and the local 60x
memory, the PowerSpan DMAs are more efficient than the local processor. They can use
bursts on both the local 60x side and on the PCI side. They use FIFOs to de-couple the PCI
bandwidth and the 60x bandwidth occupancies.
Effective Ordering of the PCI Accesses
The PowerSpan includes FIFOs between the PCI bus and the 60x bus in each direction.
When a write is done by the PCI host into the local memory, the PowerSpan can
acknowledge this write as soon as there is a place in the FIFO, but the effective write into
the local memory can be delayed, due to previous writes still waiting in the FIFO, or due to
the local 60x bus being used by the processor.
If the PCI Host makes an access to a PowerSpan register, just after this write to the local
memory, the effective completion of this register access may occur before the effective
write into the local memory. This can lead to unexpected behavior.
The order in which the PCI makes successive writes and reads into the local memory may
also not be respected on the local side. Suppose that the host makes several writes followed
by one read. Because the FIFO in the write direction may take some time to get emptied on
the local side, the effective read on the local side may happen before the last write.