Interphase Tech 4538 - Manual (Page 46)

The PCI Bridge
24 Interphase Corporation
dual port RAM, the QuadFALC framers, and the IMA device. (the processor must have its
chip selects programmed). The local space mapping is the same as when accessed by the
processor (see
PCI Local Space Mapping on page 5 ).
It is not possible to have access to the entire FLASH device when the processor is running,
because the FLASH device is an 8-bit data bus device connected to the 64-bit-only local
bus of the PowerSpan. Only bytes modulo 8 are reachable.
This problem has been neutralized for the other non-64-bit peripherals, by tying their
peripheral address bits 0 to N to local address bits 3 to N+3 respectively, so that all their
registers can be accessed on byte lane 0, at consecutive modulo 8 addresses.
When the processor is in the reset state, its memory controllers and chip-select signals are
reset, so nothing can be accessed, except the FLASH memory, for which a special
mechanism has been implemented.
N
OTE
It is possible to write from the PCI bus through a PowerSpan memory window to the
MPC8260 internal registers but it is not possible to read them. When the PowerSpan
performs a read on the 60x processor bus, it always generates a full 64-bit read.
Because most of the MPC8260 internal registers only respond to byte or word read
cycles, the returned value is 0xFFFFFFFF.
Access to the FLASH EEPROM Through CompactPCI
For FLASH in-situ re-programming through CompactPCI, there is a special FLASH mode.
In this mode, the PowerQUICC II is reset and logic generates a FLASH chip-select and
works around the problem of an 8-bit device connected to a 64-bit-only PowerSpan.
The specific FLASH mode is enabled by one of the PowerSpan interrupt pins (–INT1) used
as an output port. When –INT1 is set to 0, the PowerQUICC II is maintained in Hard Reset
state (–HRESET=0), its pins are tri-stated, the 60x bus is parked on the PowerSpan, and the
following address bus remap is implemented: the FLASH device’s low order address bits
A(2:0) are driven by the PowerSpan address bits A(24:22). This remap allows full access
to the FLASH content through byte lane 0 of the 64-bit 60x bus, provided that some address
translation is done by the software.
For more information on FLASH EEPROM device, see The FLASH EEPROM Boot
Memory on page 29 .
PCI Memory Space and I/O Space Access From the PowerQUICC II
The PowerSpan provides eight memory windows from the Local Memory space to the PCI
memory space or PCI I/O space. Each window can map a programmable size of the PCI
memory or I/O space into the PCI memory space. The size of the windows and their
enabling is set in PowerSpan registers PB_SIx_CTL, and preset at power-up: the first
window is preset by the serial EEPROM and the seven others are preset as disabled.