Interphase Tech 4538 - Manual (Page 102)

T1/E1/J1 Framer Initialization
80 Interphase Corporation
RCLK1 Configuration as TDM bus clock
8 KHz synchronization pulse generated by the internal DCO1-R circuit, synchronized to the
lines and provided to P4.
SEC/FSC Configuration
Dejittered clock generated by the internal DCO1-R circuit, synchronized to the lines and
provided to P4.
Pass-Through Mode
In multiplex direct mode, the four framers have the same rhythm. SWMODE_N = 1 and
COMCLK_N = 0.
Pass-Through mode is possible from framer 1 to framer 2, framer 3 to framer 4 and vice
versa.
System Interface
See Boot Firmware sources: tst\c\qfalc.c - Function gvQFalcInitE1PT.
The QuadFALC system multiplex mode must be disabled (GPC1.SMM = 0) with byte
interleaved format (SIC1.BIM=0), clocking rate at 2.048 MHz ( SIC1.SCC1/0=00) and
data rate at 2.048 MBit/s (SIC1.SSD1=0, FMR1.SSD0=0). Time-slot offset programming
was obtained by actual practice: XC0 = 0x00, XC1 = 0x04, RC0 = 0x00, RC1 = 0x04. The
receive buffer size must be set to two frames (SIC1.RBS1/0 = 00). The transmit buffer size
must be set to two frames (SIC1.XBS1/0 = 10). SIC3.RESX and SIC3.RESR must be set
to 0 (Synchronous Pulse Transmit (–SYPX) and Synchronous Pulse Receive
(–SYPR) are latched on first clock rising edge).
–SYPX (CMR2.IRSP = 0) and –SYPR (CMR2.IXSP = 0) inputs are mapped to XPAx and
RPAx pins respectively by setting the PC1 register to 0.
SCLKX_x (used for the transmit system clock CMR2.IXSC = 0) and SCLKR_x (used for
the receive system clock CMR2.IRSC = 0) must be configured as inputs by setting
PC5.CSXP and PC5.CSRP bits to 0.
RCLK1 Configuration as TDM Bus Clock
See Boot Firmware sources: tst\c\qfalc.c - Function gvQFalcSetPortSyncSrcPT.
RCLK1 signal of QuadFALC is recovered from the line and dejittered by DCO-R. It must
be configured as an active output (PC5.CRP = 1). Though RCLK2, RCLK3, and RCLK4
are not connected and shall be configured as inputs (PC5.CRP = 0).
RCLK1 is one of the four channels’ internally generated receive route clocks (RCLK) of a
QuadFALC: the channel selection is set with GPC1.R1S1 and GPC1.R1S0 bits – when
using RCLK1 for synchronizing the TDM SIxRAM, an active channel should be selected.
On each channel, program CMR1.RS1=1 and CMR1.RS0=0: the advantage would be to
have RCLK1 at 2.048 MHz whatever the source’s channel mode is (T1/J1 or E1), the
disadvantage is that in case of an LOS (Loss Of Signal) on the source channel, RCLK1 does