Interphase Tech 4538 - Manual (Page 85)

Chapter 2: 4538 Power-Up Initialization
4538 Hardware Reference Manual 63
• MMR =11: External bus requests are masked (PQ2 is the boot master)
• LBPC = 00: Local bus enabled
• APPC = 10: Address parity pins used for bank select
• CS10PC =01: – CS10/ – BCTL1 used as – BCTL1
• MODCK_H =0101: PLL multiplication factors: with MODCK[1:3]=111, Bus
@66, CPM @133, Core @200 MHz
PowerQUICC II Initializations
After a power-up or a reset exception, the PowerQUICC II must initialize itself and adapt
its System Interface Unit (SIU) to the 4538 hardware. It must set up its memory controllers
and Chip Selects. Then it must also initialize the SDRAM devices, before using them as its
system memory.
PowerQUICC II System Interface Unit (SIU) Initialization
The PowerQUICC II SIU includes the following elements:
• System configuration and protection
• System reset monitoring and generation
• Clock synthesizer
• Power management
• 60x bus interface
• Memory Control Units
Several registers of the SIU need to be initialized during boot time for proper operation.
Internal Memory Map Register (IMMR)
The PowerQUICC II IMMR register is normally properly set in the Reset Configuration
Word to map the PowerQUICC II Internal registers to address 0xFF010000.
Bus Configuration Register (BCR)
Some fields of the BCR register are initialized by the Reset Configuration Word. Several
other fields however, need to be initialized:
• EBM = 1: 60x bus mode
• APD = 010: Wait two cycles for ARTRY
• L2C = 0: No secondary cache
• L2D = 000: L2 cache hit delay (don’t care)
• PLDP = 0: Pipeline depth = 1
• EAV = 1: Drive full address on 60x bus
• ETM = 1: Enable Extended Transfer Mode