Interphase Tech 4538 - Manual (Page 51)

Chapter 1: Hardware Description
4538 Hardware Reference Manual 29
Vital Product Data (VPD)
No VPD has been defined for the 4538.
Interphase-Specific Production Data and Boot Monitor Parameters
Additional information concerning Interphase-specific Production Data and Boot Monitor
parameters are provided in the 4538 Built-In Self Test and Monitor Manual.
The FLASH EEPROM Boot Memory
The boot memory is a 4Mx8 AMD 29LV033 FLASH EEPROM device, placed in the 60x
bus byte lane 0. This non-volatile memory device contains the Reset Configuration Word
required by the PowerQUICC II during the power-up phase, the 4538 Interphase Boot
Firmware Code, and optionally, your own complete operational code. The FLASH memory
is always mapped at address 0xFF800000.
Depending on the FLASH memory size, the mapping of the boot firmware will be different.
There are three requirements:
• The Reset configuration must be mapped at the beginning of the FLASH memory.
• The initial vector table must be mapped at address 0xFFF00000. This address is
never in the FLASH memory, but it will wrap onto its last MB.
• The FLASH Memory is organized in sectors. The reset configuration word and the
vector table must be preserved; therefore their entire sectors will be reserved.
The various elements are/must then be mapped as follows (the FLASH addresses are
obtained by masking the local address with the flash size: for a 4MB flash device it is
0x003FFFFF).
The flash is mapped from 0xFF800000 to 0xFFFFFFFF (8MByte space). For a 4MB
device, the second 4MB space will cover the first one (see below : first and second map).
Table 1-25. FLASH EEPROM Mapping
FLASH Addr 1st MAP 2nd MAP Size Description
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