Renesas SH7641 User Manual
Sh7641
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Revision Date: Sep. 14, 2005
32
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family / SH7641 Series
SH7641
HD6417641
Rev.4.00
REJ09B0023-0400
SH7641
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
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Table of contents
Document Outline
- Cover
- Keep safety first in your circuit designs!
- Notes regarding these materials
- General Precautions on Handling of Product
- Important Notice on the Quality Assurance for this LSI
- Configuration of This Manual
- Preface
- Contents
- Figures
- Tables
- Section 1 Overview
- Section 2 CPU
- Section 3 DSP Operation
- 3.1 Data Operations of DSP Unit
- 3.1.1 ALU Fixed-Point Operations
- 3.1.2 ALU Integer Operations
- 3.1.3 ALU Logical Operations
- 3.1.4 Fixed-Point Multiply Operation
- 3.1.5 Shift Operations
- 3.1.6 Most Significant Bit Detection Operation
- 3.1.7 Rounding Operation
- 3.1.8 Overflow Protection
- 3.1.9 Data Transfer Operation
- 3.1.10 Local Data Move Instruction
- 3.1.11 Operand Conflict
- 3.2 DSP Addressing
- 3.1 Data Operations of DSP Unit
- Section 4 Clock Pulse Generator (CPG)
- Section 5 Watchdog Timer (WDT)
- Section 6 Power-Down Modes
- Section 7 Cache
- Section 8 X/Y Memory
- Section 9 Exception Handling
- Section 10 Interrupt Controller (INTC)
- 10.1 Features
- 10.2 Input/Output Pins
- 10.3 Register Descriptions
- 10.3.1 Interrupt Priority Registers B to J (IPRB to IPRJ)
- 10.3.2 Interrupt Control Register 0 (ICR0)
- 10.3.3 Interrupt Control Register 1 (ICR1)
- 10.3.4 Interrupt Control Register 3 (ICR3)
- 10.3.5 Interrupt Request Register 0 (IRR0)
- 10.3.6 Interrupt Mask Registers 0 to 10 (IMR0 to IMR10)
- 10.3.7 Interrupt Mask Clear Registers 0 to 10 (IMCR0 to IMCR10)
- 10.4 Interrupt Sources
- 10.5 INTC Operation
- 10.6 Notes on Use
- Section 11 User Break Controller (UBC)
- 11.1 Features
- 11.2 Register Descriptions
- 11.2.1 Break Address Register A (BARA)
- 11.2.2 Break Address Mask Register A (BAMRA)
- 11.2.3 Break Bus Cycle Register A (BBRA)
- 11.2.4 Break Address Register B (BARB)
- 11.2.5 Break Address Mask Register B (BAMRB)
- 11.2.6 Break Data Register B (BDRB)
- 11.2.7 Break Data Mask Register B (BDMRB)
- 11.2.8 Break Bus Cycle Register B (BBRB)
- 11.2.9 Break Control Register (BRCR)
- 11.2.10 Execution Times Break Register (BETR)
- 11.2.11 Branch Source Register (BRSR)
- 11.2.12 Branch Destination Register (BRDR)
- 11.3 Operation
- 11.4 Usage Notes
- Section 12 Bus State Controller (BSC)
- 12.1 Features
- 12.2 Input/Output Pins
- 12.3 Area Overview
- 12.4 Register Descriptions
- 12.4.1 Common Control Register (CMNCR)
- 12.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
- 12.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
- 12.4.4 SDRAM Control Register (SDCR)
- 12.4.5 Refresh Timer Control/Status Register (RTCSR)
- 12.4.6 Refresh Timer Counter (RTCNT)
- 12.4.7 Refresh Time Constant Register (RTCOR)
- 12.4.8 Reset Wait Counter (RWTCNT)
- 12.5 Operating Description
- 12.5.1 Endian/Access Size and Data Alignment
- 12.5.2 Normal Space Interface
- 12.5.3 Access Wait Control
- 12.5.4 CSn Assert Period Expansion
- 12.5.5 MPX-I/O Interface
- 12.5.6 SDRAM Interface
- 12.5.7 Burst ROM (Clock Asynchronous) Interface
- 12.5.8 Byte-Selection SRAM Interface
- 12.5.9 Burst MPX-I/O Interface
- 12.5.10 Burst ROM Interface (Clock Synchronous)
- 12.5.11 Wait between Access Cycles
- 12.5.12 Bus Arbitration
- 12.5.13 Others
- Section 13 Direct Memory Access Controller (DMAC)
- Section 14 U Memory
- Section 15 User Debugging Interface (H-UDI)
- Section 16 I2C Bus Interface 2 (IIC2)
- 16.1 Features
- 16.2 Input/Output Pins
- 16.3 Register Descriptions
- 16.3.1 I2C Bus Control Register 1 (ICCR1)
- 16.3.2 I2C Bus Control Register 2 (ICCR2)
- 16.3.3 I2C Bus Mode Register (ICMR)
- 16.3.4 I2C Bus Interrupt Enable Register (ICIER)
- 16.3.5 I2C Bus Status Register (ICSR)
- 16.3.6 Slave Address Register (SAR)
- 16.3.7 I2C Bus Transmit Data Register (ICDRT)
- 16.3.8 I2C Bus Receive Data Register (ICDRR)
- 16.3.9 I2C Bus Shift Register (ICDRS)
- 16.3.10 NF2CYC Register (NF2CYC)
- 16.4 Operation
- 16.5 Interrupt Request
- 16.6 Bit Synchronous Circuit
- 16.7 Usage Note
- Section 17 Compare Match Timer (CMT)
- Section 18 Multi-Function Timer Pulse Unit (MTU)
- 18.1 Features
- 18.2 Input/Output Pins
- 18.3 Register Descriptions
- 18.3.1 Timer Control Register (TCR)
- 18.3.2 Timer Mode Register (TMDR)
- 18.3.3 Timer I/O Control Register (TIOR)
- 18.3.4 Timer Interrupt Enable Register (TIER)
- 18.3.5 Timer Status Register (TSR)
- 18.3.6 Timer Counter (TCNT)
- 18.3.7 Timer General Register (TGR)
- 18.3.8 Timer Start Register (TSTR)
- 18.3.9 Timer Synchro Register (TSYR)
- 18.3.10 Timer Output Master Enable Register (TOER)
- 18.3.11 Timer Output Control Register (TOCR)
- 18.3.12 Timer Gate Control Register (TGCR)
- 18.3.13 Timer Subcounter (TCNTS)
- 18.3.14 Timer Dead Time Data Register (TDDR)
- 18.3.15 Timer Period Data Register (TCDR)
- 18.3.16 Timer Period Buffer Register (TCBR)
- 18.3.17 Bus Master Interface
- 18.4 Operation
- 18.5 Interrupts
- 18.6 Operation Timing
- 18.7 Usage Notes
- 18.7.1 Module Standby Mode Setting
- 18.7.2 Input Clock Restrictions
- 18.7.3 Caution on Period Setting
- 18.7.4 Conflict between TCNT Write and Clear Operations
- 18.7.5 Conflict between TCNT Write and Increment Operations
- 18.7.6 Conflict between TGR Write and Compare Match
- 18.7.7 Conflict between Buffer Register Write and Compare Match
- 18.7.8 Conflict between TGR Read and Input Capture
- 18.7.9 Conflict between TGR Write and Input Capture
- 18.7.10 Conflict between Buffer Register Write and Input Capture
- 18.7.11 TCNT2 Write and Overflow/Underflow Conflict in Cascade Connection
- 18.7.12 Counter Value during Complementary PWM Mode Stop
- 18.7.13 Buffer Operation Setting in Complementary PWM Mode
- 18.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag
- 18.7.15 Overflow Flags in Reset Sync PWM Mode
- 18.7.16 Conflict between Overflow/Underflow and Counter Clearing
- 18.7.17 Conflict between TCNT Write and Overflow/Underflow
- 18.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode
- 18.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode
- 18.7.20 Interrupts in Module Standby Mode
- 18.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection
- 18.8 MTU Output Pin Initialization
- 18.9 Port Output Enable (POE)
- Section 19 Serial Communication Interface with FIFO (SCIF)
- 19.1 Overview
- 19.2 Pin Configuration
- 19.3 Register Description
- 19.3.1 Receive Shift Register (SCRSR)
- 19.3.2 Receive FIFO Data Register (SCFRDR)
- 19.3.3 Transmit Shift Register (SCTSR)
- 19.3.4 Transmit FIFO Data Register (SCFTDR)
- 19.3.5 Serial Mode Register (SCSMR)
- 19.3.6 Serial Control Register (SCSCR)
- 19.3.7 Serial Status Register (SCFSR)
- 19.3.8 Bit Rate Register (SCBRR)
- 19.3.9 FIFO Control Register (SCFCR)
- 19.3.10 FIFO Data Count Register (SCFDR)
- 19.3.11 Serial Port Register (SCSPTR)
- 19.3.12 Line Status Register (SCLSR)
- 19.4 Operation
- 19.5 SCIF Interrupts and DMAC
- 19.6 Usage Notes
- Section 20 USB Function Module
- 20.1 Features
- 20.2 Pin Configuration
- 20.3 Register Descriptions
- 20.3.1 USB Interrupt Flag Register 0 (USBIFR0)
- 20.3.2 USB Interrupt Flag Register 1 (USBIFR1)
- 20.3.3 USB Interrupt Flag Register 2 (USBIFR2)
- 20.3.4 USB Interrupt Select Register 0 (USBISR0)
- 20.3.5 USB Interrupt Select Register 1 (USBISR1)
- 20.3.6 USB Interrupt Enable Register 0 (USBIER0)
- 20.3.7 USB Interrupt Enable Register 1 (USBIER1)
- 20.3.8 USB Interrupt Enable Register 2 (USBIER2)
- 20.3.9 USBEP0i Data Register (USBEPDR0i)
- 20.3.10 USBEP0o Data Register (USBEPDR0o)
- 20.3.11 USBEP0s Data Register (USBEPDR0s)
- 20.3.12 USBEP1 Data Register (USBEPDR1)
- 20.3.13 USBEP2 Data Register (USBEPDR2)
- 20.3.14 USBEP3 Data Register (USBEPDR3)
- 20.3.15 USBEP0o Receive Data Size Register (USBEPSZ0o)
- 20.3.16 USBEP1 Receive Data Size Register (USBEPSZ1)
- 20.3.17 USB Trigger Register (USBTRG)
- 20.3.18 USB Data Status Register (USBDASTS)
- 20.3.19 USBFIFO Clear Register (USBFCLR)
- 20.3.20 USBDMA Transfer Setting Register (USBDMAR)
- 20.3.21 USB Endpoint Stall Register (USBEPSTL)
- 20.3.22 USB Transceiver Control Register (USBXVERCR)
- 20.3.23 USB Bus Power Control Register (USBCTRL)
- 20.4 Operation
- 20.5 Processing of USB Standard Commands and Class/Vendor Commands
- 20.6 Stall Operations
- 20.7 DMA Transfer
- 20.8 Example of USB External Circuitry
- 20.9 USB Bus Power Control Method
- 20.10 Notes on Usage
- Section 21 A/D Converter
- Section 22 Pin Function Controller (PFC)
- 22.1 Register Descriptions
- 22.1.1 Port A Control Register (PACR)
- 22.1.2 Port B Control Register (PBCR)
- 22.1.3 Port C Control Register (PCCR)
- 22.1.4 Port D Control Register (PDCR)
- 22.1.5 Port E Control Register (PECR)
- 22.1.6 Port E I/O Register (PEIOR)
- 22.1.7 Port E MTU R/W Enable Register (PEMTURWER)
- 22.1.8 Port F Control Register (PFCR)
- 22.1.9 Port G Control Register (PGCR)
- 22.1.10 Port H Control Register (PHCR)
- 22.1.11 Port J Control Register (PJCR)
- 22.2 I/O Buffer Internal Block Diagram
- 22.3 Notes on Usage
- 22.1 Register Descriptions
- Section 23 I/O Ports
- Section 24 List of Registers
- Section 25 Electrical Characteristics
- 25.1 Absolute Maximum Ratings
- 25.2 DC Characteristics
- 25.3 AC Characteristics
- 25.3.1 Clock Timing
- 25.3.2 Control Signal Timing
- 25.3.3 AC Bus Timing
- 25.3.4 Basic Timing
- 25.3.5 Bus Cycle of Byte-Selection SRAM
- 25.3.6 Burst ROM Read Cycle
- 25.3.7 Synchronous DRAM Timing
- 25.3.8 Peripheral Module Signal Timing
- 25.3.9 Multi Function Timer Pulse Unit Timing
- 25.3.10 POE Module Signal Timing
- 25.3.11 I2C Module Signal Timing
- 25.3.12 H-UDI Related Pin Timing
- 25.3.13 USB Module Signal Timing
- 25.3.14 USB Transceiver Timing
- 25.3.15 AC Characteristics Measurement Conditions
- 25.4 A/D Converter Characteristics
- Appendix
- Main Revisions and Additions in this Edition
- Index
- Colophon
- Address List
- Back Cover