Renesas SH7641 User Manual
Page 542
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Section 16 I
2
C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 492 of 982
REJ09B0023-0400
TDRE
TEND
ICDRS
ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
[3] Read ICDRR
1
A
2
1
3
4
5
6
7
8
9
9
A
TRS
RDRF
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
Bit 7
Master transmit mode
Master receive mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User
processing
Data 1
Data 1
Figure 16.7 Master Receive Mode Operation Timing (1)
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