Renesas SH7641 - Manual (Page 315)

Section 11 User Break Controller (UBC)
Rev. 4.00 Sep. 14, 2005 Page 265 of 982
REJ09B0023-0400
Break Condition Specified for L Bus Data Access Cycle:
(Example 2-1)
• Register specifications
BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE,
BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000,
BRCR = H'00000080
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address: H'00123456, Address mask: H'00000000
Bus cycle: L bus/data access/read (operand size is not included in the condition)
<Channel B>
Address: H'000ABCDE, Address mask: H'000000FF
Data: H'0000A512, Data mask: H'00000000
Bus cycle: L bus/data access/write/word
On channel A, a user break occurs with longword read from address H'00123454, word read
from address H'00123456, or byte read from address H'00123456. On channel B, a user break
occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE.
(Example 2-2)
• Register specifications
BARA = H'01000000, BAMRA = H'00000000, BBRA = H'0066, BARB = H'0000F000,
BAMRB = H'FFFF0000, BBRB = H'036A, BDRB = H'00004567, BDMRB = H'00000000,
BRCR = H'00000080
Specified conditions: Channel A/channel B independent mode
<Channel A>
Address: H'01000000, Address mask: H'00000000
Bus cycle: L bus/data access/read/word
<Channel B>
Y Address: H'0000F000, Address mask: H'FFFF0000
Data: H'00004567, Data mask: H'00000000
Bus cycle: Y bus/data access/write/word
On channel A, a user break occurs during word read from address H'01000000 in the memory
space. On channel B, a user break occurs when word data H'4567 is written in address
H'0000F000 in the Y memory space. The X/Y-memory space is changed by a mode setting.