Renesas SH7641 - Manual (Page 430)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 380 of 982
REJ09B0023-0400
T2 Th Th T1 Tw
High
CKIO
A25 to A0
CSn
WEn
RD/ WR
RD
RD
D31 to D0
D31 to D0
RD/ WR
BS
DACKn*
Read
Write
Note: * The waveform for DACKn is when active low is specified.
Figure 12.39 Byte-Selection SRAM Wait Timing (BAS = 1)
(SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01)