Renesas SH7641 User Manual
Page 995
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Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 945 of 982
REJ09B0023-0400
Tc3
Tc4
Tde
Tc2
Td1
Td2
Td3
Td4
Tc1
Tr
Trw
Tp
t
CSD1
t
AD1
t
AD1
t
AD1
t
AD1
t
AD1
t
AD1
t
RWD1
t
RWD1
t
RWD1
t
CSD1
t
AD1
t
AD1
t
AD1
t
AD1
t
RASD1
t
RASD1
t
RASD1
t
RASD1
Read command
Column
address
Row
address
t
CASD1
t
CASD1
t
BSD
t
BSD
(High)
t
DQMD1
t
DQMD1
t
DACD
t
DACD
t
RDH2
t
RDS2
t
RDH2
t
RDS2
CKIO
A25 to A0
CSn
RD/
WR
A12/A11*
1
D31 to D0
RASU/L
CASU/L
BS
CKE
DQMxx
DACKn*
2
Note:
1. An address pin to be connected to pin A10 of SDRAM.
2. Waveform for
DACKn when active low is selected.
Figure 25.33 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses,
CAS Latency 2, WTRCD = 0 Cycle)
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