Texas Instruments TMS320DM644x - Manual (Page 14)

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Peripheral Architecture
2.7.3 Configuring GPIO Interrupt Edge Triggering
Each GPIO interrupt source can be configured to generate an interrupt on the GPIO signal rising edge,
falling edge, both edges, or neither edge (no event). The edge detection is synchronized to the GPIO
peripheral module clock.
The following four registers control the configuration of the GPIO interrupt edge detection:
•
The GPIO set rising edge interrupt register (SET_RIS_TRIG) enables GPIO interrupts on the
occurrence of a rising edge on the GPIO signal.
•
The GPIO clear rising edge interrupt register (CLR_RIS_TRIG) disables GPIO interrupts on the
occurrence of a rising edge on the GPIO signal.
•
The GPIO set falling edge interrupt register (SET_FAL_TRIG) enables GPIO interrupts on the
occurrence of a falling edge on the GPIO signal.
•
The GPIO clear falling edge interrupt register (CLR_FAL_TRIG) disables GPIO interrupts on the
occurrence of a falling edge on the GPIO signal.
To configure a GPIO interrupt to occur only on rising edges of the GPIO signal:
•
Write a logic 1 to the associated bit in SET_RIS_TRIG
To configure a GPIO interrupt to occur only on falling edges of the GPIO signal:
•
Write a logic 1 to the associated bit in SET_FAL_TRIG
To configure a GPIO interrupt to occur on both the rising and falling edges of the GPIO signal:
•
Write a logic 1 to the associated bit in SET_RIS_TRIG
•
Write a logic 1 to the associated bit in SET_FAL_TRIG
To disable a specific GPIO interrupt:
•
Write a logic 1 to the associated bit in CLR_RIS_TRIG
•
Write a logic 1 to the associated bit in CLR_FAL_TRIG
For detailed information on these registers, see Section 3 .
Note that the direction of the GPIO signal does not have to be an input for the interrupt event generation
to work. When a GPIO signal is configured as an output, the software can change the GPIO signal state
and, in turn, generate an interrupt. This can be useful for debugging interrupt signal connectivity.
2.7.4 GPIO Interrupt Status
The status of GPIO interrupt events can be monitored by reading the GPIO interrupt status register
(INTSTAT). Pending GPIO interrupts are indicated with a logic 1 in the associated bit position; interrupts
that are not pending are indicated with a logic 0.
For individual GPIO interrupts that are directly routed to the ARM or DSP subsystem, the interrupt status
can be read by reading the associated interrupt flag in the CPU. For the GPIO bank interrupts, INTSTAT
can be used to determine which GPIO interrupt occurred. It is the responsibility of software to ensure that
all pending GPIO interrupts are appropriately serviced.
Pending GPIO interrupt flags can be cleared by writing a logic 1 to the associated bit position in INTSTAT.
For detailed information on INTSTAT, see Section 3 .
2.7.5 Interrupt Multiplexing
No GPIO interrupts are multiplexed with other interrupt functions on the DM644x.
14 General-Purpose Input/Output (GPIO) SPRUE25 – December 2005