5 gpio set data register (set_datan), Set_data4), Section 3.5 – Texas Instruments TMS320DM644x User Manual
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3.5
GPIO Set Data Register (SET_DATAn)
Registers
The GPIO set data register (SET_DATAn) controls driving high the corresponding GPIO pin n in GPIO
bank I, if the pin is configured as an output (DIRn = 0). Writes do not affect pins not configured as GPIO
outputs. The bits in SET_DATAn are set or cleared by writing directly to this register. A read of the SETn
bit returns the output drive state of the corresponding GPIO pin n. The GPIO set data register
(SET_DATA01) is shown in
, SET_DATA23 is shown in
, SET_DATA4 is shown in
, and described in
. See
to determine the SET_DATAn bit associated with each
GPIO bank and pin number.
Figure 10. GPIO Banks 0 and 1 Set Data Register (SET_DATA01)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SET31 SET30 SET29 SET28 SET27 SET26 SET25 SET24 SET23 SET22 SET21 SET20 SET19 SET18 SET17 SET16
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SET15 SET14 SET13 SET12 SET11 SET10
SET9
SET8
SET7
SET6
SET5
SET4
SET3
SET2
SET1
SET0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 11. GPIO Banks 2 and 3 Set Data Register (SET_DATA23)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SET63 SET62 SET61 SET60 SET59 SET58 SET57 SET56 SET55 SET54 SET53 SET52 SET51 SET50 SET49 SET48
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SET47 SET46 SET45 SET44 SET43 SET42 SET41 SET40 SET39 SET38 SET37 SET36 SET35 SET34 SET33 SET32
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 12. GPIO Bank 4 Set Data Register (SET_DATA4)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
SET70 SET69 SET68 SET67 SET66 SET65 SET64
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUE25 – December 2005
General-Purpose Input/Output (GPIO)
21