Texas Instruments TMS320DM644x - Manual (Page 27)

www.ti.com
Registers
Figure 21. GPIO Bank 4 Set Rising Edge Interrupt Register (SET_RIS_TRIG4)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved SETRIS70 SETRIS69 SETRIS68 SETRIS67 SETRIS66 SETRIS65 SETRIS64
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIGn) Field Descriptions
Bit Field Value Description
31-16 SETRISn Enable rising edge interrupt detection on GPIO pin n. Reading the SETRISn bit returns the state of
pin n on GPIO bank 2I + 1. This bit field configures the GPIO pins on GPIO banks 1 and 3.
0 No effect.
1 Interrupt is caused by a low-to-high transition on GPIO pin n.
15-0 SETRISn Enable rising edge interrupt detection on GPIO pin n. Reading the SETRISn bit returns the state of
pin n on GPIO bank 2I. This bit field configures the GPIO pins on GPIO banks 0, 2, and 4.
0 No effect.
1 Interrupt is caused by a low-to-high transition on GPIO pin n.
SPRUE25 – December 2005 General-Purpose Input/Output (GPIO) 27