Texas Instruments TMS320DM644x - Manual (Page 30)

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3.10 GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIGn)
Registers
The GPIO set falling edge interrupt register (SET_FAL_TRIGn) enables a falling edge on the GPIO pin to
generate a GPIO interrupt. The GPIO set falling edge interrupt register (SET_FAL_TRIG01) is shown in
Figure 25 , SET_FAL_TRIG23 is shown in Figure 26 , SET_FAL_TRIG4 is shown in Figure 27 , and
described in Table 14 . See Table 1 to determine the SET_FAL_TRIGn bit associated with each GPIO
bank and pin number.
Figure 25. GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (SET_FAL_TRIG01)
31 30 29 28 27 26 25 24
SETFAL31 SETFAL30 SETFAL29 SETFAL28 SETFAL27 SETFAL26 SETFAL25 SETFAL24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
SETFAL23 SETFAL22 SETFAL21 SETFAL20 SETFAL19 SETFAL18 SETFAL17 SETFAL16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
SETFAL15 SETFAL14 SETFAL13 SETFAL12 SETFAL11 SETFAL10 SETFAL9 SETFAL8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
SETFAL7 SETFAL6 SETFAL5 SETFAL4 SETFAL3 SETFAL2 SETFAL1 SETFAL0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 26. GPIO Banks 2 and 3 Set Falling Edge Interrupt Register (SET_FAL_TRIG23)
31 30 29 28 27 26 25 24
SETFAL63 SETFAL62 SETFAL61 SETFAL60 SETFAL59 SETFAL58 SETFAL57 SETFAL56
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
SETFAL55 SETFAL54 SETFAL53 SETFAL52 SETFAL51 SETFAL50 SETFAL49 SETFAL48
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
SETFAL47 SETFAL46 SETFAL45 SETFAL44 SETFAL43 SETFAL42 SETFAL41 SETFAL40
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
SETFAL39 SETFAL38 SETFAL37 SETFAL36 SETFAL35 SETFAL34 SETFAL33 SETFAL32
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
30 General-Purpose Input/Output (GPIO) SPRUE25 – December 2005