Texas Instruments TMS320DM644x - Manual (Page 4)

List of Figures
1 GPIO Peripheral Block Diagram ........................................................................................... 9
2 Peripheral Identification Register (PID) .................................................................................. 17
3 GPIO Interrupt Per-Bank Enable Register (BINTEN)
..................................................................
18
4 GPIO Banks 0 and 1 Direction Register (DIR01) ...................................................................... 19
5 GPIO Banks 2 and 3 Direction Register (DIR23) ...................................................................... 19
6 GPIO Bank 4 Direction Register (DIR4)
.................................................................................
19
7 GPIO Banks 0 and 1 Output Data Register (OUT_DATA01) ......................................................... 20
8 GPIO Banks 2 and 3 Output Data Register (OUT_DATA23) ......................................................... 20
9 GPIO Bank 4 Output Data Register (OUT_DATA4)
...................................................................
20
10 GPIO Banks 0 and 1 Set Data Register (SET_DATA01) ............................................................. 21
11 GPIO Banks 2 and 3 Set Data Register (SET_DATA23) ............................................................. 21
12 GPIO Bank 4 Set Data Register (SET_DATA4)
.......................................................................
21
13 GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01) .......................................................... 23
14 GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23) .......................................................... 23
15 GPIO Bank 4 Clear Data Register (CLR_DATA4)
.....................................................................
23
16 GPIO Banks 0 and 1 Input Data Register (IN_DATA01) .............................................................. 25
17 GPIO Banks 2 and 3 Input Data Register (IN_DATA23) .............................................................. 25
18 GPIO Bank 4 Input Data Register (IN_DATA4)
........................................................................
25
19 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (SET_RIS_TRIG01) .................................... 26
20 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register (SET_RIS_TRIG23) .................................... 26
21 GPIO Bank 4 Set Rising Edge Interrupt Register (SET_RIS_TRIG4)
..............................................
27
22 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG01) ................................. 28
23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG23) ................................. 28
24 GPIO Bank 4 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG4)
............................................
29
25 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (SET_FAL_TRIG01) ................................... 30
26 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register (SET_FAL_TRIG23) ................................... 30
27 GPIO Bank 4 Set Falling Edge Interrupt Register (SET_FAL_TRIG4)
..............................................
31
28 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG01) ................................. 32
29 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG23) ................................. 32
30 GPIO Bank 4 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG4)
...........................................
33
31 GPIO Banks 0 and 1 Interrupt Status Register (INTSTAT01) ........................................................ 34
32 GPIO Banks 2 and 3 Interrupt Status Register (INTSTAT23) ........................................................ 34
33 GPIO Bank 4 Interrupt Status Register (INTSTAT4)
..................................................................
35
List of Figures 4 SPRUE25 – December 2005