Texas Instruments TMS320DM644x - Manual (Page 32)

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3.11 GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn)
Registers
The GPIO clear falling edge interrupt register (CLR_FAL_TRIGn) disables a falling edge on the GPIO pin
from generating a GPIO interrupt. The GPIO clear falling edge interrupt register (CLR_FAL_TRIG01) is
shown in
Figure 28 , CLR_FAL_TRIG23 is shown in Figure 29 , CLR_FAL_TRIG4 is shown in Figure 30 ,
and described in Table 15 . See Table 1 to determine the CLR_FAL_TRIGn bit associated with each GPIO
bank and pin number.
Figure 28. GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG01)
31 30 29 28 27 26 25 24
CLRFAL31 CLRFAL30 CLRFAL29 CLRFAL28 CLRFAL27 CLRFAL26 CLRFAL25 CLRFAL24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
CLRFAL23 CLRFAL22 CLRFAL21 CLRFAL20 CLRFAL19 CLRFAL18 CLRFAL17 CLRFAL16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
CLRFAL15 CLRFAL14 CLRFAL13 CLRFAL12 CLRFAL11 CLRFAL10 CLRFAL9 CLRFAL8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
CLRFAL7 CLRFAL6 CLRFAL5 CLRFAL4 CLRFAL3 CLRFAL2 CLRFAL1 CLRFAL0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 29. GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG23)
31 30 29 28 27 26 25 24
CLRFAL63 CLRFAL62 CLRFAL61 CLRFAL60 CLRFAL59 CLRFAL58 CLRFAL57 CLRFAL56
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
CLRFAL55 CLRFAL54 CLRFAL53 CLRFAL52 CLRFAL51 CLRFAL50 CLRFAL49 CLRFAL48
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
CLRFAL47 CLRFAL46 CLRFAL45 CLRFAL44 CLRFAL43 CLRFAL42 CLRFAL41 CLRFAL40
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
CLRFAL39 CLRFAL38 CLRFAL37 CLRFAL36 CLRFAL35 CLRFAL34 CLRFAL33 CLRFAL32
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
32 General-Purpose Input/Output (GPIO) SPRUE25 – December 2005