Texas Instruments TMS320C3x - Manual (Page 446)

DMA Controller
12-67 Peripherals
- Source and destination synchronization (SYNC = 1 1)
When SYNC = 1 1, the DMA is synchronized to both the source and
destination. A read is performed when an interrupt is received. Then, a
write is performed on the following interrupt. Figure 12–46 shows source
and destination synchronization when SYNC = 1 1.
Figure 12–46. Mechanism for DMA Source and Destination Synchronization
Start
Disable DMA interrupts globally
DMA channel performs a read
DMA channel performs a write
Go to start
Idle until enabled interrupt is received
Enable DMA interrupts globally
Idle until enabled interrupt is received
Disable DMA interrupts globally
Enable DMA interrupts globally
Clear corresponding IF bit
Clear corresponding IF bit
12.3.8 DMA Memory Transfer Timing
The ’C30 and ’C31 devices provide one DMA channel, while the ’C32 device
provides two DMA channels. The maximum data transfer rate that the ’C3x
DMA sustains is one word every two cycles. In the ’C32, the two DMA channels
transfer data in a sequential time-slice fashion, rather than simultaneously,
because the two channels share one common set of busses.