Texas Instruments TMS320C3x - Manual (Page 750)

Index
Index-9
interface
enhanced memory, TMS320C32 2-19
expansion bus 2-19
primary bus 2-19
interlocked
instructions 2-21
operations 7-13–7-20
busy-waiting loop 7-15
external flag pins (XF0, XF1) 7-13
instructions 13-5–13-6
instructions used in 7-13
LDFI and LDII instructions 7-14
loads and stores 7-13
multiprocessor counter manipulation 7-16
STFI and STII instructions 7-14
internal
bus operation 2-18
buses 2-8
clock 12-10
interrupt 7-26
definitions D-4
enable register, definition D-4
interrupt 7-26–7-37
acknowledge, instruction (IACK) 13-107
acknowledge signal, definition D-4
considerations
TMS320C30 7-44–7-47
TMS320C3x 7-41–7-43
control bits 7-32
interrupt enable register (IE) 7-32
interrupt flag register (IF) 7-32
status register (ST) 7-32
CPU/DMA interaction 7-40
definition D-4
DMA 7-38, 12-64
edge-triggered 12-64
external 2-21, 7-36
flag register (IF), behavior 7-32
initialization 7-47
latency (CPU) 7-35–7-36
locations 3-15
logic, functional diagram 7-37
prioritization 7-31
processing 7-33–7-35
block diagram 7-34, 7-39
serial port 12-34
receive timer 12-34
transmit timer 12-34
interrupt (continued)
service routine (ISR) 7-35, 7-50
instruction 7-35
timer 12-2, 12-13
vector table
TMS320C30 and TMS320C31 7-26–7-28
TMS320C32 7-29–7-30
interrupt and trap
branch instructions, TMS320C31, microcomputer
mode 4-17
vector locations, TMS320C32 4-18, 7-30
interrupt service routine (ISR), definition D-4
interrupt-enable (IE) register
bits defined 3-10
CPU register file 3-9
interrupt-trap table pointer (ITTP) 3-14
definition D-4
interrupts, level-triggered 12-64
IOSTRB
bus cycles 10-42
control register 10-9
signal 9-3, 9-15
ISR. See interrupt service routine (ISR)
L
LA0-LA30, definition D-8
latched
floating-point underflow condition flag 13-29
overflow condition flag 13-29
LD0-LD31, definition D-8
LDFI instruction 7-14
LDII instruction 7-14
load
data-page pointer instruction (LDP) 13-134
floating-point
exponent instruction (LDE) 13-112
mantissa instruction (LDM) 13-133
value
(LDF) 13-114
conditionally instruction (LDFcond) 13-115
interlocked instruction (LDFI) 13-117
integer
conditionally instruction (LDIcond) 13-125
instruction (LDI) 13-123
interlocked instruction (LDII) 13-127
load and store instructions 13-2