Texas Instruments TMS320C3x - Manual (Page 102)

Instruction Cache
4-20
Figure 4–12. Instruction-Cache Architecture
Segment start
address registers Segment words
LRU
Stack
SSA register 0 Segment word 0
Segment word 1
Segment word 30
Segment word 31
Segment word 0
Segment word 1
Segment word 30
Segment word 31
MRU segment number
LRU segment number
Segment 0
Segment 1
P
flags
0
1
30
31
0
1
30
31
32
19
SSA register 1
The LRU stack determines which of the two segments qualifies as the least
recently used after each access to the cache. Each time a segment is accessed,
its segment number is removed from the LRU stack and pushed onto the top
of the LRU stack. Therefore, the number at the top of the stack is the most re-
cently used (MRU) segment number, and the number at the bottom of the stack
is the least recently used segment number.
At reset, the LRU stack is initialized with 0 at the top and 1 at the bottom. All
P flags in the instruction cache are cleared.
When a replacement is necessary, the LRU segment is selected for replace-
ment. Also, the 32 P flags for the segment to be replaced are set to 0, and the
segment’s SSA register is replaced with the 19 MSBs of the instruction address.