Subi3||sti – Texas Instruments TMS320C3x User Manual
Page 695
Parallel SUBI3 and STI
SUBI3||STI
13-237
Assembly Language Instructions
Syntax
SUBI3
src1, src2, dst1
||
STI
src3, dst2
Operation
src2 – src1
→
dst1
||
src3
→
dst2
Operands
src1
register (R
n1, 0
≤
n1
≤
7)
src2
indirect (
disp = 0, 1, IR0, IR1)
dst1
register (R
n2, 0
≤
n2
≤
7)
src3
register (R
n3, 0
≤
n3
≤
7)
dst2
indirect (
disp = 0, 1, IR0, IR1)
This instruction’s operands have been augmented in the following devices:
-
’C31 silicon revision 6.0 or greater
-
’C32 silicon revision 2.0 or greater
src1
register (R
n1, 0
≤
n1
≤
7)
src2
indirect (
disp = 0, 1, IR0, IR1) or any CPU register
dst1
register (R
n2, 0
≤
n2
≤
7)
src3
register (R
n3, 0
≤
n3
≤
7)
dst2
indirect (
disp = 0, 1, IR0, IR1)
Opcode
31
24 23
16
8 7
0
15
1 1
1 0 1
0
dst1
1
src1
dst2
src2
src3
Description
An integer subtraction and an integer store are performed in parallel. All regis-
ters are read at the beginning and loaded at the end of the execute cycle. This
means that if one of the parallel operations (STI) reads from a register and the
operation being performed in parallel (SUBI3) writes to the same register, STI
accepts the contents of the register as input before it is modified by the SUBI3.
If
src3 and dst1 point to the same location, src3 is read before the write to dst1.
Cycles
1
Status Bits
These condition flags are modified only if the destination register is R7 – R0.
LUF
Unaffected
LV
1 if an integer overflow occurs; unchanged otherwise
UF
0
N
1 if a negative result is generated; 0 otherwise
Z
1 if a 0 result is generated; 0 otherwise
V
1 if an integer overflow occurs; 0 otherwise
C
1 if a borrow occurs; 0 otherwise
OVM
Operation is affected by OVM bit value.
Mode Bit