Texas Instruments TMS320C3x - Manual (Page 463)

Instruction Set
13-5 Assembly Language Instructions
Table 13–4. Program-Control Instructions
Instruction Description Instruction Description
B cond Branch conditionally (standard) IDLE Idle until interrupt
B condD Branch conditionally (delayed) NOP No operation
BR Branch unconditionally (standard) RETI cond Return from interrupt conditionally
BRD Branch unconditionally (delayed) RETS cond Return from subroutine conditionally
CALL Call subroutine RPTB Repeat block of instructions
CALL cond Call subroutine conditionally RPTS Repeat single instruction
DB cond Decrement and branch conditionally
(standard) SWI Software interrupt
DB condD Decrement and branch conditionally
(delayed) TRAP cond Trap conditionally
IACK Interrupt acknowledge
13.1.5 Low-Power Control Instructions
The low-power control instruction group consists of three instructions that affect
the low-power modes. The low-power idle (IDLE2) instruction allows extremely
low-power mode. The divide-clock-by-16 (LOPOWER) instruction reduces the
rate of the input clock frequency. The restore-clock-to-regular-speed
(MAXSPEED) instruction causes the resumption of full-speed operation.
Table 13–5 lists the low-power control instructions.
Table 13–5. Low-Power Control Instructions
Instruction Description Instruction Description
IDLE2 Low-power idle MAXSPEED Restore clock to regular speed
LOPOWER Divide clock by 16
13.1.6 Interlocked-Operations Instructions
The five interlocked-operations instructions (Table 13–6) support multi-
processor communication and the use of external signals to allow for powerful
synchronization mechanisms. They also ensure the integrity of the communi-
cation and result in a high-speed operation. Refer to Chapter 7 for examples
of the use of interlocked instructions.