Texas Instruments TMS320C3x - Manual (Page 84)

Memory
4-2
4.1 Memory
The ’C3x accesses a total memory space of 16M (million) 32-bit words of pro-
gram, data, and I/O space and allows tables, coefficients, program code, or
data to be stored in either RAM or ROM. In this way, you can maximize memory
usage and allocate memory space as desired.
RAM blocks 0 and 1 are each 1K 32 bits on the ’C30 and ’C31. The ROM
block is 4K 32 bits on the ’C30. The ’C31 and ’C32 have a boot ROM. By
manipulating one external pin (MC/MP or MCBL/MP), you can configure the first
1000h words of memory to address the on-chip ROM or external RAM. Each on-
chip RAM and ROM block can support two CPU accesses in a single cycle. The
separate program buses, data buses, and DMA buses allow for parallel program
fetches, data reads/writes, and DMA operations, which are covered in Chap-
ter 11,
Peripherals.
4.1.1 Memory Maps
The following sections describe the memory maps for the ’C30, ’C31, and
’C32.
4.1.1.1 TMS320C30 Memory Map
The memory map depends on whether the processor is running in micro-
processor mode (MC/MP = 0) or microcomputer mode (MC/MP = 1). The
memory maps for these modes are similar (see Figure 4–1 on page 4-4).
Locations 800000h–801FFFh are mapped to the expansion bus. When this
region is accessed, MSTRB is active. Locations 802000h–803FFFh are
reserved. Locations 804000h–805FFFh are mapped to the expansion bus.
When this region is accessed, IOSTRB is active. Locations 806000h–
807FFFh are reserved. All of the memory-mapped peripheral bus registers
are in locations 808000h–8097FFh. In both modes, RAM block 0 is located
at addresses 809800h–809BFFh, and RAM block 1 is located at addresses
809C00h–809FFFh. Locations 80A000h–0FFFFFFh are accessed over the
external memory port (STRB active).
- Microprocessor Mode
In microprocessor mode, the 4K on-chip ROM is not mapped into the ’C3x
memory map. Locations 0h–03Fh consist of interrupt vector, trap vector,
and reserved locations, all of which are accessed over the external memory
port (STRB active) (see Figure 4–1 on page 4-4). Locations
040h–7FFFFFh are also accessed over the external memory port.