Texas Instruments TMS320C3x - Manual (Page 413)

Serial Ports
12-34
When the serial port is placed in the handshake mode, the insertion and deletion
of a leading 1 for transmitted data, the sending of a 0 for acknowledgement of
received data, and the waiting for this acknowledge bit are all performed auto-
matically. Using this scheme, it is simple to connect processors with no external
hardware and to guarantee secure communication. Figure 12–25 is a typical
configuration.
In the handshake mode, FSX is automatically configured as an output. Con-
tinuous mode is automatically disabled. After a system reset or XRESET, the
transmitter is always permitted to transmit. The transmitter and receiver must
be reset when entering the handshake mode.
Figure 12–25. Direct Connection Using Handshake Mode
CLKX
FSX
DX
CLKR
FSR
DR
’C3x #1 ’C3x #2
CLKR
FSR
DR
CLKX
FSX
DX
12.2.11 Serial-Port Interrupt Sources
A serial port has the following interrupt sources:
- Transmit-timer interrupt. The rising edge of XTSTAT causes a single-
cycle interrupt pulse to occur. When XTINT is 0, this interrupt pulse is
disabled.
- Receive-timer interrupt. The rising edge of RTSTAT causes a single-
cycle interrupt pulse to occur. When RTINT is 0, this interrupt pulse is
disabled.
- Transmitter-interrupt. Occurs immediately following a DXR-to-XSR
transfer. The transmitter interrupt is a single-cycle pulse. When the serial-
port global-control register bit XINT is 0, this interrupt pulse is disabled.
- Receiver-interrupt. Occurs immediately following an RSR-to-DRR trans-
fer. The receiver interrupt is a single-cycle pulse. When the serial-port
global-control register bit RINT is 0, this interrupt pulse is disabled.
The transmit-timer interrupt pulse is ORed with the transmitter interrupt pulse
to create the CPU-transmit interrupt flag XINT. The receive-timer interrupt pulse
is ORed with the receiver interrupt pulse to create the CPU receive-interrupt flag
RINT.