Texas Instruments TMS3320C5515 - Manual (Page 16)

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modes.
• Three 32-bit timers with 16-bit prescaler; one timer supports watchdog functionality.
• A USB 2.0 slave.
• A 10-bit successive approximation (SAR) analog-to-digital converter with touchscreen conversion
capability.
• One real-time clock (RTC) with associated low power mode.
1.2 System Memory
The DSP supports a unified memory map (program code sections and data sections can be mixed and
interleaved within the entire memory space) composed of both on-chip and external memory. The on-chip
memory consists of 320KB of RAM and 128KB of ROM.
The external memory interface (EMIF) port provides the means for the DSP to access external memory
and devices including: mobile and non-mobile single data rate (SDR) SDRAM, (for limitations, see note in
Section 1.1.5 ), NOR Flash, NAND Flash and SRAM.
Separate from the program and data space, the DSP also includes a 64K-byte I/O space for peripheral
registers.
1.2.1 Program/Data Memory Map
The device provides 16MB of total address space composed of on-chip RAM, on-chip ROM, and external
memory space supporting a variety of memory types. The on-chip, dual-access RAM allows two accesses
to a given block during the same cycle. The device has 8 blocks of 8K-bytes of dual-access RAM. The
on-chip, single-access RAM allows one access to a given block per cycle. The device has 32 blocks of
8K-bytes of single-access RAM. Attempts to perform two accesses in a cycle to single-access memory will
cause one access to stall until the next cycle. An access is defined as either a read or write operation. For
the most efficient use of DSP processing power (MIPS), it is important to pay attention to the memory
blocks that are being simultaneously accessed by the code and data operations.
The external memory space is divided into five spaces. Each space has a chip select decode signal
(called CS) that indicates an access to the selected space. The external memory interface (EMIF)
supports access to asynchronous memories such as SRAM Flash, mobile SDRAM and SDRAM.
The DSP memory is accessible by different master modules within the DSP, including the device CPU, the
four DMA controllers, and the USB. The DSP memory map as seen by these modules is illustrated in
Figure 1-2 .
16 System Control SPRUFX5A – October 2010 – Revised November 2010
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