Texas Instruments TMS3320C5515 - Manual (Page 33)

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1.5 Power Management
1.5.1 Overview
In many applications there may be specific requirements to minimize power consumption for both power
supply (and battery) and thermal considerations. There are two components to power consumption: active
power and leakage power. Active power is the power consumed to perform work and, for digital CMOS
circuits, scales roughly with clock frequency and the amount of computations being performed. Active
power can be reduced by controlling the clocks in such a way as to either operate at a clock frequency
just high enough to complete the required operation in the required time-line or to run at a high enough
clock frequency until the work is complete and then drastically cut the clocks (that is, to bypass mode or
clock gate) until additional work must be performed.
Leakage power is due to static current leakage and occurs regardless of the clock rate. Leakage, or
standby power, is unavoidable while power is applied and scales roughly with the operating junction
temperatures. Leakage power can only be avoided by removing power completely.
The DSP has several means of managing the power consumption, as detailed in the following sections.
There is extensive use of automatic clock gating in the design as well as software-controlled module clock
gating to not only reduce the clock tree power, but to also reduce module power by freezing its state while
not operating. Clock management enables you to slow the clocks down on the chip in order to reduce
switching power. Independent power domains allow you to shut down parts of the DSP to reduce static
power consumption. When not being used, the internal memory of the DSP can also be placed in a low
leakage power mode while preserving the memory contents. The operating voltage and drive strength of
the I/O pins can also be reduced to decrease I/O power consumption.
Table 1-19 summarizes all of the power management features included in the DSP.
Table 1-19. Power Management Features
Power Management Features Description
Clock Management
PLL power-down The system PLL can be powered-down when not in use to
reduce switching and bias power.
Peripheral clock idle Peripheral clocks can be idled to reduce switching power.
Dynamic Power Management
Core Voltage Scaling The DSP LDO and DSP logic support two voltage ranges to
allow voltage adjustments on-the-fly, increasing voltage during
peak processing power demand and decreasing during low
demand.
Static Power Management
DARAM/SARAM low power modes The internal memory of the DSP can be placed in a low leakage
power mode while preserving memory contents.
Independent power domains DSP Core (CV
DD
) and USB Core (USB_V
DD1P3
, USB_V
DDA1P3
)
can be shut off while other supplies remain powered.
I/O Management
I/O voltage selection The operating voltage and/or slew rate of the I/O pins can be
reduced (at the expense of performance) to decrease I/O power
consumption.
USB power-down The USB peripheral can be powered-down when not being
used.
1.5.2 Power Domains
The DSP has separate power domains which provide power to different portions of the device. The
separate power domains allow the user to select the optimal voltage to achieve the lowest power
consumption at the best possible performance. Note that several power domains have similar voltage
requirements and, therefore, could be grouped under a single voltage domain.
33 SPRUFX5A – October 2010 – Revised November 2010 System Control
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