Texas Instruments TMS3320C5515 - Manual (Page 25)

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When the PLL is powered up (PLL_PWRDN = 0), the PLL will start its phase-locking sequence. You must
keep the clock generator in BYPASS MODE for at least 4 mS while the phase-locking sequence is
ongoing. See
Section 1.4.3.2 for more details on the PLL_MODE of the clock generator.
1.4.2.3 CLKOUT Pin
For debug purposes, the DSP includes a CLKOUT pin which can be used to tap different clocks within the
clock generator. The SRC bits of the CLKOUT control source register (CCSSR) can be used to specify the
source for the CLKOUT pin (see
Figure 1-5 and Table 1-6 ).
NOTE: There is no internal logic to prevent glitches while changing the CLKOUT source. Also there
is no provision for internally dividing down the CLKOUT frequency other than the options
inherently available for selecting the CLKOUT source.
The CLKOUT pin's output driver is enabled/disabled through the CLKOFF bit of the CPU ST3_55 register.
At hardware reset, CLKOFF is cleared to 0 so that the clock is visible for debug purposes. But within the
bootloader romcode, CLKOFF is set to 1 to conserve power. After the bootloader finishes, the customer
application code is free to re-enable CLKOUT. For more information on the ST3_55 register, see the
TMS320C55x 3.0 CPU Reference Guide (
SWPU073 ).
The slew rate (i.e., dV/dt) of the CLKOUT pin can be controlled by the CLKOUTSR bits in the output slew
rate control register (OSRCR). This feature allows for additional power savings when the CLKOUT pin
does not need to drive large loads.
Figure 1-5. CLKOUT Control Source Select Register (CCSSR) [1C24h]
15 4 3 0
Reserved SRC
R-0 R/W-Bh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-6. CLKOUT Control Source Select Register (CCSSR) Field Descriptions
Bit Field Value Description
15-4 Reserved 0 Reserved.
3-0 SRC CLKOUT source bits. These bits specify the source clock for the CLKOUT pin.
0 CLKOUT pin outputs System PLL output clock, PLLOUT.
1h CLKOUT pin is set high.
2h CLKOUT pin outputs System PLL output clock, PLLOUT.
3h CLKOUT pin is set low.
4h CLKOUT pin outputs System PLL output clock, PLLOUT.
5h CLKOUT pin is set low.
6h CLKOUT pin outputs System PLL output clock, PLLOUT.
7h CLKOUT pin outputs USB PLL output clock.
8h CLKOUT pin outputs System PLL output clock, PLLOUT.
9h CLKOUT pin outputs SAR clock.
Ah CLKOUT pin outputs System PLL output clock, PLLOUT.
Bh CLKOUT pin outputs system clock, SYSCLK (default mode).
Ch CLKOUT pin outputs System PLL output clock, PLLOUT.
Dh Reserved, do not use.
Eh CLKOUT pin outputs System PLL output clock, PLLOUT.
Fh CLKOUT pin outputs USB PLL output clock.
25 SPRUFX5A – October 2010 – Revised November 2010 System Control
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