Texas Instruments TMS3320C5515 - Manual (Page 23)

www.ti.com System Clock Generator
1.3.2 Clock Domains
The device has many clock domains defined by individually disabled portions of the clock tree structure.
Understanding the clock domains and their clock enable/disable control registers is very important for
managing power and for ensuring clocks are enabled for domains that are needed. By disabling the clocks
and thus the switching current in portions of the chip that are not used, lower dynamic power consumption
can be achieved and prolonging battery life.
Figure 1-3 shows the clock tree structure with the clock gating represented by the AND gates. Each AND
gate shows the controlling register that allows the downstream clock signal to be enabled/disabled. Once
disabled most clock domains can be re-enabled, when the associated clock domain logic is needed, via
software running on the CPU. But some domains actually stop the clocks to the CPU and therefore
software running on the CPU cannot be responsible for re-enabling those clock domains. Other
mechanism must exist for restarting those clocks, and the specific cases are listed below:
• The System Clock Generator (PLL) can be powered-down by writing a 1 to PLL_PWRDN bit in the
clock generator control register CGCR1. This stops the PLL from oscillating and shuts down its analog
circuits. It is important to bypass the System Clock Generator by writing 0 to SYSCLKSEL bit in CCR2
(clock confguration register 2) prior to powering it down, else the CPU will loose its clock and not be
able to recover without hardware reset.
NOTE: Failsafe logic exists to prevent selecting the PLL clock if it has been powered down but this
logic does not protect against powering down the PLL while it is selected as the system clock
source. Therefore, software should always maintain responsibility for bypassing the PLL prior
to and whenever it is powered down.
• The SYSCLKDIS bit in PCGCR1 [clock gating control register 1) is the master clock gater. Asserting
this bit causes the main system clock, SYSCLK, to stop and, therefore, the CPU and all peripherals no
longer receive clocks. The WAKEUP pin, INT0 & INT1 pin, or RTC interrupt can be used to re-enable
the clock from this condition.
• The ICR bit in CPUI(clock gating control register) gates clocks to the CPU and uses the CPU’s idle
instruction to initiate the clock off mode. Any non-masked interrupt can be used to re-enable the CPU
clocks.
1.4 System Clock Generator
1.4.1 Overview
The system clock generator ( Figure 1-4 ) features a software-programmable PLL multiplier and several
dividers. The clock generator accepts an input clock from the CLKIN pin or the output clock of the
real-time clock (RTC) oscillator. The clock generator offers flexibility and convenience by way of
software-configurable multiplier and divider to modify the clock rate internally. The resulting clock output,
SYSCLK, is passed to the CPU, peripherals, and other modules inside the DSP.
A set of registers are provided for controlling and monitoring the activity of the clock generator. You can
write to the SYSCLKSEL bit in CCR2 register to toggle between the two main modes of operation:
• In the BYPASS MODE (see Section 1.4.3.1 ), the entire clock generator is bypassed, and the frequency
of SYSCLK is determined by CLKIN or the RTC oscillator output. Once the PLL is bypassed, the PLL
can be powered down to save power.
• In the PLL MODE (see Section 1.4.3.2 ), the input frequency can be both multiplied and divided to
produce the desired SYSCLK frequency, and the SYSCLK signal is phase-locked to the input clock
signal (CLKREF).
The clock generator bypass mux (controlled by SYSCLKSEL bit in CCR2 register) is a glitchfree mux,
which means that clocks will be switched cleanly and not short cycle pulses when switching among the
BYPASS MODE and PLL MODE.
For debug purposes, the CLKOUT pin can be used to see different clocks within the clock generator. For
details, see
Section 1.4.2.3 .
23 SPRUFX5A – October 2010 – Revised November 2010 System Control
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