Texas Instruments TMS320C6457 - Manual (Page 11)

www.ti.com Using the Address Registers
2 Using the Address Registers
The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for write
operations (HPIAW). These roles are unchanging from the position of the HPI DMA logic. HPI DMA logic
collects the address from HPIAR when reading from DSP internal/external memory and collects the
address from HPIAW when writing to DSP internal/external memory.
However, unlike the HPI DMA logic, the host can choose how to interact with the two HPIA registers.
Using the DUALHPIA bit of HPIC, the host determines whether HPIAR and HPIAW act as a single 32-bit
register (single-HPIA mode) or as two independent 32-bit registers (dual-HPIA mode).
CAUTION
The host must always write a word address to the HPIAs. For example, L2
memory has a base byte address of 80 0000h that corresponds to a word
address of 20 0000h. A host must write 20 0000h to the HPIA register to point
the HPI to the base of L2 memory.
2.1 Single-HPIA Mode
If DUALHPIA = 0 in HPIC, HPIAR and HPIAW become a single HPIA register for the host. In this mode:
•
A host HPIA write cycle (HCNTL[1:0] = 10b, HR/W = 0) updates HPIAR and HPIAW with the same
value.
• Both HPIA registers are incremented during autoincrement read/write cycles (HCNTL[1:0] = 01b).
• An HPIA read cycle (HCNTL[1:0] = 10b, HR/W = 1) returns the contents of HPIAR, which should be
identical to the contents of HPIAW.
To maintain consistency between the contents of HPIAR and HPIAW, the host should always re-initialize
the HPIA registers after changing the state of the DUALHPIA bit. In addition, when DUALHPIA = 0, the
host must always re-initialize the HPIA registers when it changes the data direction (from an HPID read
cycle to an HPID write cycle, or vice versa). Otherwise, the memory location accessed by the HPI DMA
logic might not be the host's intended location.
2.2 Dual-HPIA Mode
The host can take advantage of two independent HPIA registers by choosing the dual-HPIA mode
(DUALHPIA = 1 in HPIC). In this mode:
•
A host HPIA access (HCNTL[1:0] = 10b) reads/updates either HPIAR or HPIAW, depending on the
value of the HPIA read/write select (HPIARWSEL) bit of HPIC. This bit is programmed by the host.
While HPIARWSEL = 1, only HPIAR is read or updated by the host. While HPIARWSEL = 0, only
HPIAW is read or updated by the host. The HPIARWSEL bit is only meaningful in the dual-HPIA mode.
NOTE: The HPIARWSEL bit does not affect the HPI DMA logic. Regardless of the value of
HPIARWSEL, the HPI DMA logic uses HPIAR when reading from memory and HPIAW when
writing to memory.
• A host HPID access with autoincrementing (HCNTL[1:0] = 01b) causes only the relevant HPIA value to
be incremented to the next consecutive memory address. In an autoincrement read cycle, HPIAR is
incremented after it has been used to perform the current read from memory. In an autoincrement write
cycle, HPIAW is incremented after it has been used for the write operation.
11 SPRUGK7A – March 2009 – Revised July 2010 Host Port Interface (HPI)
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