Texas Instruments TMS320C6457 - Manual (Page 33)

www.ti.com FIFOs and Bursting
If the host initiates an HPID read cycle with autoincrementing, the HPI DMA logic performs two 4-word
burst operations to fill the read FIFO. The host is initially held off by the deassertion of the HRDY signal
until data is available to be read from the read FIFO. Once data is available in the read FIFO, the host can
read data from the read FIFO by performing subsequent reads of HPID with autoincrementing. Once the
initial read has been performed, the HPI DMA logic continues to perform 4-word burst operations to
consecutive memory addresses every time there are four empty word locations in the read FIFO. The HPI
DMA logic continues to prefetch data to keep the read FIFO full, until the occurrence of an event that
causes a read FIFO flush (see
Section 6.3 ).
As mentioned, read bursting may also begin with a FETCH command. The host should always precede
the FETCH command with the initialization of the HPIAR register or a non-autoincrement access, so that
the read FIFO is flushed beforehand. When the host initiates a FETCH command, the HPI DMA logic
begins to prefetch data to keep the read FIFO full, as described in the previous paragraph. The FETCH bit
in HPIC does not actually store the value that is written to it; rather, the decoding of a host write of 1 to
this bit is considered a FETCH command.
The FETCH command can be helpful if the host does not use the HRDY signal. The host can initiate
prefetching by writing 1 to the FETCH bit and then poll the HRDY bit, which is also in HPIC. When the
HRDY bit is 1, the host can perform an HPID read cycle. See
Section 4 for more details on the HRDY bit.
Both types of continuous or burst reads described previously begin with a write to the HPI address
register, which causes a read FIFO flush. This is the typical way of initiating read cycles, because the
initial read address needs to be specified.
An HPID read cycle without autoincrementing does not initiate any prefetching activity. Instead, it causes
the read FIFO to be flushed and causes the HPI DMA logic to perform a single-word read from the
processor memory. As soon as the host activates a read cycle without autoincrementing, prefetching
activity ceases until the occurrence of a FETCH command or an autoincrement read cycle. A
non-autoincrement read cycle always should be preceded by another non-autoincrement cycle or the
direct initialization of HPIAR, so that the read FIFO is flushed beforehand.
6.2 Write Bursting
A write to the write address register (HPIAW) causes the write FIFO to be flushed. This means that any
write data in the write FIFO is forced to its destination in the processor memory (the HPI DMA logic
performs burst operations until the write FIFO is empty). When the FIFO has been flushed, the only action
that will cause the HPI DMA logic to perform burst writes is a host write to HPID with autoincrementing.
The initial host-write data is stored in the write FIFO. An HPI DMA write is not requested until there are
four words in the write FIFO. As soon as four words have been written to the FIFO via the HPID write
cycles with autoincrementing, the HPI DMA logic performs a 4-word burst operation to the processor
memory. The burst operations continue as long as there are at least four words in the FIFO. If the FIFO
becomes full (eight words are waiting in the FIFO), the HPI holds off the host by deasserting HRDY until at
least one empty word location is available in the FIFO.
Because excessive time might pass between consecutive burst operations, the HPI has a time-out
counter. If there are fewer than four words in the write FIFO and the time-out counter expires, the HPI
DMA logic empties the FIFO immediately by performing a 2-word or 3-word burst, or a single-word write,
as necessary. Every time new data is written to the write FIFO, the time-out counter is automatically reset
to begin its count again. The time-out period is 256 internal clock cycles. See the device-specific data
manual to determine how the HPI is clocked on your device.
An HPID write cycle without autoincrementing does not initiate any bursting activity. Instead, it causes the
write FIFO to be flushed and causes the HPI DMA logic to perform a single-word write to the processor
memory. As soon as the host activates a write cycle without autoincrementing, bursting activity ceases
until the occurrence of an autoincrement write cycle. A non-autoincrement write cycle always should be
preceded by the initialization of HPIAW or by another non-autoincrement access, so that the write FIFO is
flushed beforehand.
33 SPRUGK7A – March 2009 – Revised July 2010 Host Port Interface (HPI)
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