Texas Instruments TMS320C6457 - Manual (Page 34)

FIFOs and Bursting www.ti.com
6.3 FIFO Flush Conditions
When specific conditions occur within the HPI, the read or write FIFO must be flushed to prevent the
reading of stale data from the FIFOs. When a read FIFO flush condition occurs, all current host accesses
and direct memory accesses (DMAs) to the read FIFO are allowed to complete. This includes DMAs that
have been requested but not yet initiated. The read FIFO pointers are then reset, causing any read data to
be discarded.
Similarly, when a write FIFO flush condition occurs, all current host accesses and DMAs to the write FIFO
are allowed to complete. This includes DMAs that have been requested but not yet initiated. All posted
writes in the FIFO are then forced to completion with a final burst or single-word write, as necessary.
If the host initiates an HPID host cycle during a FIFO flush, the cycle is held off with the deassertion of
HRDY until the flush is complete and the FIFO is ready to be accessed.
The following conditions cause the read and write FIFOs to be flushed:
•
Read FIFO flush conditions:
– A value from the host is written to the read address register (HPIAR)
– The host performs an HPID read cycle without autoincrementing
• Write FIFO flush conditions:
– A value from the host is written to the write address register (HPIAW)
– The host performs an HPID write cycle without autoincrementing
– The write-burst time-out counter expires
When operating with DUALHPIA = 0 (all HPIA writes and increments affect both HPIAR and HPIAW), any
read or write flush condition causes both read and write FIFOs to be flushed. In addition, the following
scenarios cause both FIFOs to be flushed when DUALHPIA = 0:
• The host performs an HPID write cycle with autoincrementing while the read FIFO is not empty (the
read FIFO still contains data from prefetching or an HPID read cycle with autoincrementing).
• The host performs an HPID read cycle with autoincrementing while the write FIFO is not empty (there
is still posted write data in the write FIFO).
This is useful in providing protection against reading stale data by reading a memory address when a
previous write cycle has not been completed at the same address. Similarly, this protects against
overwriting data at a memory address when a previous read cycle has not been completed at the same
address.
When operating with DUALHPIA = 1 (HPIAR and HPIAW are independent), there is no such protection.
However, when DUALHPIA = 1, data flow can occur in both directions without flushing both FIFOs
simultaneously, thereby improving HPI bandwidth.
6.4 FIFO Behavior When a Hardware Reset or Software Reset Occurs
A hardware reset (device-level reset) or an HPI software reset (HPIRST = 1 in HPIC) causes the FIFOs to
be reset. The FIFO pointers are cleared, so that all data in the FIFOs are discarded. In addition, all
associated FIFO logic is reset.
If a host cycle is active when a hardware or HPI software reset occurs, the HRDY signal is asserted
(driven low), allowing the host to complete the cycle. When the cycle is complete, HRDY is deasserted
(driven high). Any access interrupted by a reset may result in corrupted read data or a lost write data (if
the write does not actually update the intended memory or register). Although data may be lost, the host
interface protocol is not violated. While either of reset condition is true, and the host is idle (internal
HSTRB is held high), the FIFOs are held in reset, and host transactions are held off with an inactive
HRDY signal.
34 Host Port Interface (HPI) SPRUGK7A – March 2009 – Revised July 2010
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