1 summary of the hpi registers – Texas Instruments TMS320C6457 User Manual
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Introduction to the HPI
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The HPI uses multiplexed operation, meaning the data bus carries both address and data. When the host
drives an address on the bus, the address is stored in the address register (HPIA) in the HPI, so that the
bus can then be used for data.
The HPI supports two interface modes: HPI16 and HPI32 mode. DSP selects either HPI16 or HPI32 mode
via the HPI_WIDTH device configuration pin at reset.
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16-bit multiplexed mode (HPI16). The HPI is called HPI16 when operating as a 16-bit wide host port.
This mode is selected if the HPI_WIDTH configuration pin of the DSP is sampled low at reset. In this
mode, a 16-bit data bus (HD[15:0]) carries both addresses and data. HPI16 combines successive
16-bit transfers to provide 32-bit data to the CPU. The halfword identification line (HHWIL) input is
used on the HPI16 to identify the first or second half word of a word transfer.
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32-bit multiplexed mode (HPI32). HPI operates in this mode as a 32-bit wide host port. This mode is
selected if the HPI_WIDTH configuration pin of the DSP is sampled high at reset. In this mode, a 32-bit
data bus (HD[31:0]) carries both addresses and data. HHWIL is not applicable for HPI32 mode.
The HPI contains two HPIAs (HPIAR and HPIAW), which can be used as separate address registers for
read accesses and write accesses (for details, see
A 32-bit control register (HPIC) is accessible by the DSP CPU and the host. The CPU can use HPIC to
send an interrupt request to the host, to clear an interrupt request from the host, and to monitor the HPI.
The host can use HPIC to configure and monitor the HPI, to send an interrupt request to the CPU, and to
clear an interrupt request from the CPU.
Data flow between the host and the HPI uses a temporary storage register, the 32-bit data register (HPID).
Data arriving from the host is held in HPID until the data can be stored elsewhere in the DSP. Data to be
sent to the host is held in HPID until the HPI is ready to perform the transfer. When address
autoincrementing is used, read and write FIFOs are used to store burst data. If autoincrementing is not
used, the FIFO memory acts as a single register (only one location is used).
NOTE:
To manage data transfers between HPID and the internal memory, the DSP contains
dedicated HPI DMA logic. The HPI DMA logic is not programmable. It automatically stores or
fetches data using the address provided by the host. The HPI DMA logic is independent of
the EDMA3 controller included in the DSP.
In the DSP system, master and slave peripherals communicate with each other via the Switched Central
Resource (SCR). By definition, master peripherals are capable of initiating read and write transfers in the
system and may not solely rely on the EDMA3 controller for their data transfers. Slave peripherals rely on
the EDMA3 controller to perform transfers. The HPI is a master peripheral; it uses its DMA logic to directly
communicate with the rest of the system via the SCR and does not rely on the EDMA3 controller for its
data transfers. Note that the HPI cannot access all DSP resources or peripherals; see the device-specific
data manual for a list of resources accessible through the HPI.
1.1
Summary of the HPI Registers
summarizes the registers inside the HPI, including access permissions and access requirements
from the perspective of the host and the DSP CPU. See
for detailed descriptions of all these
registers.
describes the two address registers (HPIAW and HPIAR) and describes the two HPIA
modes that determine how the host uses these registers.
The host can only access HPIC, HPIAW, HPIAR, and HPID. By driving specific levels on the HCNTL[1:0]
signals, the host indicates whether it is performing an HPIC, HPIA, or HPID access. For an HPID access,
the HCNTL signals also indicate whether or not the HPI should perform an automatic address increment
after the access.
describes the effects of the HCNTL[1:0] signals. The HR/W signal indicates
whether the host is reading or writing.
The DSP CPU cannot access HPID but has limited access to HPIC, HPIAR, and HPIAW. The CPU has
full access to the power and emulation management register, which selects an emulation mode for the
HPI.
HPI registers accessible by the CPU have an address in the DSP memory map.
shows the offset
addresses for various HPI registers. See the device-specific data manual for the base addresses of the
HPI registers.
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Host Port Interface (HPI)
SPRUGK7A – March 2009 – Revised July 2010
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