Texas Instruments TMS320C6457 - Manual (Page 29)

www.ti.com Software Handshaking Using the HPI Ready (HRDY) Bit
4 Software Handshaking Using the HPI Ready (HRDY) Bit
In addition to the HRDY output signal, the HPI contains an HRDY bit in the control register (HPIC). This bit
is useful for software polling when the host does not have an input pin to connect to the HRDY pin. In
some cases, the host can read the HPIC register and, based on the status of the HRDY bit, determine
whether the HPI is ready with read data (during a read cycle) or ready to latch write data (during a write
cycle).
Section 4.1 explains which read cycles and write cycles allow for polling of the HRDY bit.
NOTE: Software handshaking using the HRDY bit is not supported on all devices. See your
device-specific data manual to determine if this functionality is supported on your device.
When the host is performing HPID host cycles with an automatic address increment between accesses,
the value in the HRDY bit refers to the availability of space in the write FIFO or the availability of data in
the read FIFO. If the previous host cycle was a read cycle, the HRDY bit refers to the read FIFO. If the
previous host cycle was a write cycle, the HRDY bit refers to the write FIFO. If the previous host cycle set
the FETCH bit of HPIC, the HRDY bit refers to the read FIFO. If the host has performed no data accesses
yet, the HRDY bit refers to the write FIFO by default.
The HRDY bit reflects the level of an internal HRDY signal that is not gated by the chip select (HCS) input.
The HRDY bit could be cleared in response to one of the following conditions:
•
A prefetch was issued (FETCH = 1 in HPIC). HRDY is low until a flush occurs and new data is loaded
in the read FIFO. When the data is available, the HRDY bit is set.
• The previous cycle was an autoincrement HPID write cycle, and the write FIFO became full. When
space is available in the write FIFO, the HRDY bit is set.
• The previous cycle was a non-autoincrement HPID write cycle and the write FIFO is not empty. This
condition indicates that the data has not yet been written to memory.
• The previous cycle was an HPID read cycle and the read FIFO is empty. Exception: If the previous
cycle was a non-autoincrement HPID read cycle, when internal HSTRB becomes high (inactive), the
HRDY bit stays 1 even though the FIFO is empty. This exception accommodates hosts that require the
HPI to indicate that it is ready before the host begins the next cycle.
• The previous cycle was an HPID read cycle and a read FIFO flush is in progress.
4.1 Polling the HRDY Bit
Read cycles. Only the FETCH command and autoincrement HPID read cycles may perform reads in this
mode while using HRDY polling. Fixed address mode HPID read cycles may not be performed because
during cycles in fixed address mode, the host must extend the read cycle until the read FIFO is flushed
and the read data is retrieved from the DSP memory. Therefore, the host cannot create the HPIC cycles
needed to poll HRDY because the host bus is busy with the current read access. The difference in a cycle
with autoincrementing is that the host can release the host bus while the read data is automatically loaded
into the read FIFO (due to the FETCH command and subsequent autoincrement read cycles).
Write cycles. As long as the HRDY bit is sampled high (and refers to write FIFO status), any type of write
cycle may be performed by the host. This includes autoincrement HPID write cycles and fixed address
mode HPID write cycle. It is possible to do either type of HPID cycle because the write data goes into the
FIFO, and the internal transfer to DSP memory takes place after the host has ended the host bus cycle.
This leaves the host bus inactive and available to the host for HPIC reads to poll the HRDY bit.
29 SPRUGK7A – March 2009 – Revised July 2010 Host Port Interface (HPI)
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