Texas Instruments TMS320C6457 - Manual (Page 35)

www.ti.com Emulation and Reset Considerations
7 Emulation and Reset Considerations
7.1 Emulation Modes
The FREE and SOFT bits of the power and emulation management register (PWREMU_MGMT)
determine the response of the HPI to an emulation suspend condition. If FREE = 1, the HPI is not
affected, and the SOFT bit has no effect. If FREE = 0 and SOFT = 0, the HPI is not affected. If FREE = 0
and SOFT = 1:
•
The HPI DMA logic halts after the current host and HPI DMA operations are completed.
• The external host interface functions as normal throughout the emulation suspend condition. The host
may access the control register (HPIC). In the 16-bit and 32-bit multiplexed modes, the host may also
access the HPIA registers and may perform data reads until the read FIFO is empty or data writes until
the write FIFO is full. As in normal operation, the HRDY pin is driven high during a host cycle that
cannot be completed due to the write FIFO being full or the read FIFO being empty. If this occurs,
HRDY continues to be driven high, holding off the host, until the emulation suspend condition is over
and the FIFOs are serviced by the HPI DMA logic, allowing the host cycle to complete.
• When the emulation suspend condition is over, the appropriate requests by the HPI DMA logic are
made to process any posted host writes in the write FIFO or to fill the read FIFO as necessary. HPI
operation then continues as normal.
7.2 Software Reset Considerations
The control register (HPIC) provides an HPI software reset bit (HPIRST) that is used to reset the read and
write FIFOs. When the CPU sets the HPIRST bit:
•
If the internal strobe signal, internal HSTRB, is high (host is inactive), HRDY is driven high and remains
high until the reset condition is over.
• If internal HSTRB is low (host cycle is active), direct memory accesses (DMAs) of the FIFOs are
allowed to complete. Then HRDY is driven low, allowing the host to complete the cycle. When internal
HSTRB goes high (cycle is complete), HRDY is driven high and remains high until the reset condition
is over. If the active cycle was a write cycle, the memory or register may not have been correctly
updated. If the active cycle was a read cycle, the fetched value may not be valid.
• After any remaining DMAs of the FIFOs are complete, the read and write FIFOs and the associated
FIFO logic are reset. The FIFO pointers are cleared, so that any data in the FIFOs are discarded. The
CPU reads 0 in HPIRST until the FIFOs are fully reset. Writing 0 to HPIRST before the FIFO reset is
complete will not stop the FIFO reset from occurring.
An HPI software reset does not reset any HPI registers other than the FIFOs.
7.3 Hardware Reset Considerations
When the DSP is reset:
• If the internal strobe signal, internal HSTRB, is high (host is inactive), HRDY is driven high and remains
high until the reset condition is over.
• If internal HSTRB is low (host cycle is active), HRDY is driven low, allowing the host to complete the
cycle. When internal HSTRB goes high (cycle is complete), HRDY is driven high and remains high until
the reset condition is over. If the active cycle was a write cycle, the memory or register may not have
been correctly updated. If the active cycle was a read cycle, the fetched value may not be valid.
• The HPI registers are reset to their default values. These default values are shown under each bit field
of the register figures in
Section 8 .
• The read and write FIFOs and the associated FIFO logic are reset (this includes a flush of the FIFOs).
• Host-to-CPU and CPU-to-host interrupts are cleared.
35 SPRUGK7A – March 2009 – Revised July 2010 Host Port Interface (HPI)
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