Texas Instruments TMS320C6457 - Manual (Page 40)

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8.4 Host Port Interface Address Registers (HPIAW and HPIAR)
There are two 32-bit HPIA registers: HPIAW for write operations and HPIAR for read operations. The HPI
can be configured such that HPIAW and HPIAR act as a single 32-bit HPIA (single-HPIA mode) or as two
separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the host. For details about these HPIA
modes, see
Section 2 .
Figure 32 and Figure 33 show the format of an address register during host and CPU accesses. As shown
in the figures, the host has full read/write access to the HPIAs, while the CPU can only read the HPIAs.
CAUTION
The host must always write a word address to the HPIAs. For example, L2
memory has a base byte address of 80 0000h that corresponds to a word
address of 20 0000h. A host must write 20 0000h to the HPIA register to point
the HPI to the base of L2 memory.
Figure 32. Format of an Address Register (HPIAW or HPIAR) - Host Access Permissions
31-0
ADDRESS
R/W-0
LEGEND: R = Read only; W = Write; -n = value after reset
Figure 33. Format of an Address Register (HPIAW or HPIAR) - CPU Access Permissions
31-0
ADDRESS
R-0
LEGEND: R = Read only; -n = value after reset
Table 9. Host Port Interface Address Registers (HPIAW or HPIAR) Field Descriptions
Bit Field Value Description
31-0 ADDRESS Read/write address. The host must initiate this field with a word address.
40 Host Port Interface (HPI) SPRUGK7A – March 2009 – Revised July 2010
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